Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Khato]

This workload loads the whole socket so you're sitting at TDP cap.

So the 9754 is showing 1.25X the performance of the 6766E at 1.44x the power consumption. As expected, SRF wins on efficiency until it's pushed too far, eg the 6780E. Will be quite interesting to see how the actual high core count variants of SRF scale.

 

[adroc_thurston]

So the 9754 is showing 1.25X the performance of the 6766E at 1.44x the power consumption

It's also like that much perf over the 330W SRF.
Come on.

 

[Saylick]

High Yield has an excellent video summarizing LNL so I’ll gladly give him a plug:

One thing he mentions that wasn’t covered too much by others is the 8 MB memory side cache. It is shared amongst much of the uncore but it primarily acts as a LLC for the Skymont cluster, which explains how Skymont is able to hit such high IPC because, according to the video, Skymont would be starved without it.

 

[poke01]

High Yield has an excellent video summarizing LNL so I’ll gladly give him a plug:

One thing he mentions that wasn’t covered too much by others is the 8 MB memory side cache. It is shared amongst much of the uncore but it primarily acts as a LLC for the Skymont cluster, which explains how Skymont is able to hit such high IPC because, according to the video, Skymont would be starved without it.

High Yields really good. Not biased but presents info well. No drama too

 

[gdansk]

One thing he mentions that wasn’t covered too much by others is the 8 MB memory side cache. It is shared amongst much of the uncore but it primarily acts as a LLC for the Skymont cluster, which explains how Skymont is able to hit such high IPC because, according to the video, Skymont would be starved without it.

LLC? Oh no the Strix Point people are gonna be mad at Microsoft again

 

[adroc_thurston]

It is shared amongst much of the uncore but it primarily acts as a LLC for the Skymont cluster, which explains how Skymont is able to hit such high IPC because, according to the video, Skymont would be starved without it.

It's a high IPC increase over the tortured poor 2c LP cluster of MTL.
The one with 2MB of L2 and then a nice, deep pit of main mem.

Gonna be a lot more mid over the DT Gracemont with 4megs of L2 and a full LLC backing it.

 

[poke01]

One thing he mentions that wasn’t covered too much by others is the 8 MB memory side cache. It is shared amongst much of the uncore but it primarily acts as a LLC for the Skymont cluster, which explains how Skymont is able to hit such high IPC because,

Bit like Apples P core and it’s L2 Cache? Should probably watch the video first…

 

[adroc_thurston]

Bit like Apples P core and it’s L2 Cache?

No, Apple has an SLC too, just a slightly different one.
Their LITTLEs are also like 4megs of L2 and then the SLC pile.

 

[Saylick]

It's a high IPC increase over the tortured poor 2c LP cluster of MTL.
The one with 2MB of L2 and then a nice, deep pit of main mem.

Fair point, but that IPC increase is comparable to Redwood Cove in MTL regardless.

 

[Saylick]

Alright, I’m calling it a day.

Lots of news to digest in these exciting times!

 

[invisible_city]

Sierra Forest might be the ticket to getting confidence back in Xeon. If GNR over performs expectations similarly to SRF there might be legit competition in x86 DataCenter again.

GNR will be interesting.

The biggest takeaway from Computex for me, besides the painful wall of partners crap, is that Intel is awake and AMD thought that wouldn’t happen for a while. Exciting times for the industry, competition has been so helpful for both companies. Nvidia is next.

 

[gdansk]

I was fine with NPUs when they weren't so big. But Lunar Lake could be 4+8 easily if it had 1/2 as many NPU units.
Now it's starting to look a bit silly...

 

[H433x0n]

Gonna be a lot more mid over the DT Gracemont with 4megs of L2 and a full LLC backing it.

ARL-S Skymont that’s attached to the ring outperforms RPC clock for clock. How is that mid?

 

[Khato]

It's also like that much perf over the 330W SRF.
Come on.

So what? Pretty sure sales of the 'overclocked' 330W 6780E are going to be pretty pathetic compared to the 250W 6766E. For the target market all that matters is 'good enough' performance and best efficiency possible. Comparisons favor SRF even further for use cases where HT is disabled.

 

[H433x0n]

So what? Pretty sure sales of the 'overclocked' 330W 6780E are going to be pretty pathetic compared to the 250W 6766E. For the target market all that matters is 'good enough' performance and best efficiency possible. Comparisons favor SRF even further for use cases where HT is disabled.

Who knew it’d be Intel atoms saving x86 in client and in data center.

 

[adroc_thurston]

ARL-S Skymont that’s attached to the ring outperforms RPC clock for clock. How is that mid?

Cuz it's not that much faster than Gracemonts with fat caches.

Pretty sure sales of the 'overclocked' 330W 6780E are going to be pretty pathetic compared to the 250W 6766E. For the target market all that matters is 'good enough' performance and best efficiency possible. Comparisons favor SRF even further for use cases where HT is disabled.

Meta runs 200W Bergamos. Untouchable efficiency. Now what?
Like lmao, at least try.

 

[H433x0n]

Cuz it's not that much faster than Gracemonts with fat caches.

How does that math work?

 

[Khato]

Meta runs 200W Bergamos. Untouchable efficiency. Now what?
Like lmao, at least try.

Simple, lower power SRF. Or do you not know about the SRF Meta SKU with your supposed extensive insider knowledge? What's the TDP?

 

[adroc_thurston]

How does that math work?

L2 bumps were bonanza for atoms.
Don't think anyone ran SIR 1 copy on GRT that I can easily access so sozz.

 

[adroc_thurston]

Simple, lower power SRF. Or do you not know about the SRF Meta SKU with your supposed extensive insider knowledge? What's the TDP?

They're 144c and still 200W and Bergamo still wins.
Please.

 

[Doug S]

Yeah, Hardwareluxx says N3b.
It's N3b.

Why would "Hardwareluxx" know what the node is?

Did Intel actually say "N3B", or say "it is the same node as Apple M3"? Or are people just saying "N3B" if they believed the past claims of N3B, and saying N3E because they know that's available now?

Unless it is confirmed by either Intel or TSMC, I'm not going to believe claims of either one until a semi research firm gets their hands on one and puts it under an electron microscope.

 

[adroc_thurston]

Why would "Hardwareluxx" know what the node is?

They're the press and they were on the event.
Simple enough?

Did Intel actually say "N3B", or say "it is the same node as Apple M3"?

They tell the press the spec sheet so yeah.

 

[invisible_city]

It's a high IPC increase over the tortured poor 2c LP cluster of MTL.
The one with 2MB of L2 and then a nice, deep pit of main mem.

Gonna be a lot more mid over the DT Gracemont with 4megs of L2 and a full LLC backing it.

Low effort fud LLM fine tuned on hype train Zen posts.

 

[adroc_thurston]

Low effort fud LLM fine tuned on hype train

2/10 bait.
You're going lower.

 

[H433x0n]

View attachment 100430
L2 bumps were bonanza for atoms.
Don't think anyone ran SIR 1 copy on GRT that I can easily access so sozz.

Have you seen the slide deck where they compare Skymont directly to RPC? It’s clear as day.