Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Hulk]

This is the quote from RWT: "Supposedly Willamette, the 180nm P4, actually had all the necessary circuitry for SMT present, but it was disabled due to the difficulty of validating SMT until the tail end of the Northwood 130nm generation."

While in some ways what you said are true, in other ways the Netburst-based chips were very narrow and had even less opportunities to take advantage of SMT. So on wider chips you have more opportunities due to more execution units. On Netburst you had more stalls, which potentially gives you more chance for a benefit, but that depends on if you have enough execution resources.

In short, Netburst turned out to be a marketing driven design which was unrealistic, and thus to make up for the deficiencies added conflicting design choices.

If you go back to the graph of performance gains using HT for both Netburst and Nehalem, Nehalem has many cases where the gains are far greater. Netburst unlike Nehalem had quite a few scenarios where you lost performance whereas the latter would gain a small amount.

Ultimately the impending demise of HT on consumer chips at least may be driven by two factors:
1. Lowering future execution risk.
2. Amdahl's Law benefitting larger fewer core processors over smaller many core processors. Hence, a 64-core Zen 4 makes sense but a 256-core E core chip does not.

Good information and clarification.

The race to 1GHz and clock speed in general was of immense importance around the turn of the century. Intel was obviously quite embarrassed that AMD made it to 1GHz first and they did it with a core that arguably had better IPC. Eventually this led to the overclocked P3 1.13GHz fiasco.

This stung Intel and I have a feeling the PR department and sales people in general DEMANDED processors that could regain the frequency crown and keep it permanently. I'm sure the engineers tried to tell them about the importance of IPC and the problems that would come about with extremely long pipelines required for high clocks, power/heat issues, and other frequency scaling issues, and were probably summarily shut down. We want high clocks!!!

It was a wrong turn for Intel. They got "lost" for a while and finally got back on track with Conroe.

 

[igor_kavinski]

I look forward to an Intel core that does not race to 100C and then throttles.

 

[Thibsie]

It was a wrong turn for Intel. They got "lost" for a while and finally got back on track with Conroe.

Nah, P4 Mobile was a lot better idea. In that era, the only CPU able to empty your battery as fast as light and as hot as Tokamak xD

 

[Hulk]

Nah, P4 Mobile was a lot better idea. In that era, the only CPU able to empty your battery as fast as light and as hot as Tokamak xD

Hey but at least no radiation exposure.

 

[H433x0n]

I look forward to an Intel core that does not race to 100C and then throttles.

That’s the new normal for both companies going forward. If anything ARL will be even harder to cool due to heat density.

 

[coercitiv]

Hey but at least no radiation exposure.

Debatable, we have yet to determine the cause of your occasional transformation.

 

[DavidC1]

If by wider we mean many available execution units then Goldmont (etc) sounds like a good match for SMT with all its execution units. But it deliberately doesn't have it. Are the execution units too limited? Or is the dual decoder approach enough to keep execution units busy without needing SMT?

Well, the P cores are better fit for it. The E cores have more ports because they are all dedicated, while the ports are shared for P cores. In a way they are following the ARM camp because they do something similar which also doesn't use HT. The P cores have less ports but they are more powerful.

Also the P cores have a longer pipeline stage, thus more stalls. And it has more OoOE resources.

 

[zir_blazer]

This is the quote from RWT: "Supposedly Willamette, the 180nm P4, actually had all the necessary circuitry for SMT present, but it was disabled due to the difficulty of validating SMT until the tail end of the Northwood 130nm generation."

I'm almost positively sure that I mentioned SOMEWHERE around here that Willamatte had HT functional on the Xeon Foster MP. You only didn't saw it on the consumer Pentium 4.
Also, W9x had no APIC support at all thus it couldn't see anything beyond a single physical core, and Windows XP was almost a year away from P4 launch, so where you wanted to use HT in (Besides the obvious answer of Windows 2000, which is unlikely to be a mainstream consumer first choice)?

 

[Thibsie]

Mmm, I was sure Willamette had no HT at all but could be wrong of course.

 

[DavidC1]

The mention of 0.18u P4's having HT was from Anandtech article by the way.

 

[naukkis]

Mmm, I was sure Willamette had no HT at all but could be wrong of course.

Willamette Xeon was called Foster - and it had HT enabled.

 

[naukkis]

This is the quote from RWT: "Supposedly Willamette, the 180nm P4, actually had all the necessary circuitry for SMT present, but it was disabled due to the difficulty of validating SMT until the tail end of the Northwood 130nm generation."

While in some ways what you said are true, in other ways the Netburst-based chips were very narrow and had even less opportunities to take advantage of SMT. So on wider chips you have more opportunities due to more execution units. On Netburst you had more stalls, which potentially gives you more chance for a benefit, but that depends on if you have enough execution resources.

Netburst was little bit of braindead design as most of resources that could be benefit SMT was used by stupid recall mechanism - if instruction data wasn't ready instead of waiting data to be ready Netburst re-issued instruction repeatedly until it's data arrived. No wonder that those cpu's run hot and didn't benefit much from SMT.

 

[dullard]

Videocardz found a Dell XPS roadmap leak. https://videocardz.com/newz/exclusi...ake-laptops-in-2026-nova-lake-systems-in-2027 The leak's source material was made nearly a year ago, so things may no longer be the same dates, but it does provide some possible timelines.

Note: these are the Dell XPS targets, not necessarily the date the Intel chips are launched. But in order to hit these targets, Intel would have to launch before these dates.

• Lunar Lake-MX: Aug / Sept 2024
• Arrow Lake-H: Feb / Mar 2025
• Panther Lake-H: Feb / Mar 2026
• Nova Lake: Q1 2027

 

[tamz_msc]

I think that Lunar Lake being adopted so soon is likely why Dell at least has been real quiet about their XPS lineup with MTL.

 

[Gideon]

Chips and Cheese looks at Crestmont (Meteor Lake's E-cores):

Meteor Lake’s E-Cores: Crestmont Makes Incremental Progress

Efficiency cores, or E-Cores for short, sit front and center in Intel’s consumer CPU strategy.

chipsandcheese.com

 

[igor_kavinski]

If anyone has downloaded the Scribd pdf, can you please upload it to google drive and share? https://videocardz.com/newz/exclusi...ake-laptops-in-2026-nova-lake-systems-in-2027

 

[SteinFG]

Intel Core Ultra "Arrow Lake-S" desktop lineup leak: 24-core 285K, 20-core 265K and 14-core 245K - VideoCardz.com

Intel to launch three K-Series SKUs in Arrow Lake-S lineup The information comes from Benchlife. The site has already leaked plenty of Intel products in the past, including the 14th Gen Core series with full clock speed disclosure when they were still under a domain of rumors. The media has now...

videocardz.com

Wanna comment a bit on that leak. Benchlife says there's going to be 3 K processors, 5 regular processors, and 5 T processors. Thus VC editor speculates that there's 2 F prcessors in there. I have another take: Intel will just get the i9/i7/i5 chips from last gen, and release similar arrow lake configurations, but without F-series SKUs. It lines up:

	CPU	Cores	Base TDP
K chip, 1	14900K	8 + 16	125W
K chip, 2	14700K	8 + 12	125W
K chip, 3	14600K	6 + 8	125W
Regular, 1	14900	8 + 16	65W
Regular, 2	14700	8 + 12	65W
Regular, 3	14600	6 + 8	65W
Regular, 4	14500	6 + 8	65W
Regular, 5	14400	6 + 4	65W
T chip, 1	14900T	8 + 16	35W
T chip, 2	14700T	8 + 12	35W
T chip, 3	14600T	6 + 8	35W
T chip, 4	14500T	6 + 8	35W
T chip, 5	14400T	6 + 4	35W

 

[DavidC1]

Chips and Cheese looks at Crestmont (Meteor Lake's E-cores):

Meteor Lake’s E-Cores: Crestmont Makes Incremental Progress

Efficiency cores, or E-Cores for short, sit front and center in Intel’s consumer CPU strategy.

chipsandcheese.com

The larger TLB support is beneficial for Sierra Forest.

Rest are basically summarized as Gracemont but with 6-wide instead of 5-wide backend, which Sierra Glen does not have.

The "2 year gap" C&C points out is because Raptorlake was meant to be a filler. The original roadmap would have been Alder-->Meteor. This is due to the 7nm(Now Intel 4) delay.

Note: these are the Dell XPS targets, not necessarily the date the Intel chips are launched. But in order to hit these targets, Intel would have to launch before these dates.

Basically everything launches at CES except Lunarlake which we might see Intel flaunting it in about a month at Computex.

The schedules are absolutely nothing new to me. Clockwork, 1 year launch cycle every generation which is said to be an "optimal balance between product lifecycle and R&D costs".

 

[igor_kavinski]

OK guys. Throw at me all the technical reasons you can muster for WHY these silicon companies cannot release an already released product with updated CPU blocks? Like why couldn't the RPL-R be a real refresh and feature Crestmont cores? It's really frustrating to think what could have been

 

[DavidC1]

OK guys. Throw at me all the technical reasons you can muster for WHY these silicon companies cannot release an already released product with updated CPU blocks? Like why couldn't the RPL-R be a real refresh and feature Crestmont cores? It's really frustrating to think what could have been

-Because one uses a very different layout meant for monolithic designs and the other doesn't?
-The new one is on a completely new process?
-The predecessor is on a heavily refined version of the process used since 2020, even sacrificing some density to so, meaning a new process would inevitably result in LOWER performance even if it has better uarch?

And one can't ignore the financial and marketing aspects. Such as avoiding sunk costs on a smaller volume(desktop) market and getting more per dollar by skipping a massive change to hasten the release for the true next gen(Arrowlake).

 

[igor_kavinski]

true next gen(Arrowlake).

But it won't be monolithic so the tile latency overhead will still be there. Intel should've started small, mastered the art of disaggregated tiles on netbook CPUs or something and then applied their experience to a mass market product. Now the consumers have to be their guinea pigs and continue being so until they are able to catch up to AMD level of latency masking. Meteor Lake's worst case core to core latency is 152ns while 7950X's worst case is 78ns (both from AT reviews). Is ARL gonna be able to get it under 100ns? Meanwhile RPL's worst case is 53.5 which even AMD can't achieve so Intel is going towards a permanent (unless a miracle happens) future core to core latency downgrade. The original x86 company trying desperately to mimic their competitor with complete disregard for logic and sense.

 

[coercitiv]

Throw at me all the technical reasons you can muster for WHY these silicon companies cannot release an already released product with updated CPU blocks? Like why couldn't the RPL-R be a real refresh and feature Crestmont cores?

Because it wouldn't be a refresh anymore. It would not hit the mark in terms of the sales & development cycle. (or even worse, it would delay the proper new gen products)

Remember desktop Broadwell, that full lineup that never made it to market because it was so late that Skylake took over? That's all the technical reasons you need.

 

[dullard]

Basically everything launches at CES except Lunarlake which we might see Intel flaunting it in about a month at Computex.

The schedules are absolutely nothing new to me. Clockwork, 1 year launch cycle every generation which is said to be an "optimal balance between product lifecycle and R&D costs".

Exactly. Yearly launches shouldn't surprise anyone. But after years of people repeatedly posting here that the 5 nodes in 4 years won't happen, it is nice to see that there are actually plans for it to happen.

 

[DavidC1]

But it won't be monolithic so the tile latency overhead will still be there. Intel should've started small, mastered the art of disaggregated tiles on netbook CPUs or something and then applied their experience to a mass market product. Now the consumers have to be their guinea pigs and continue being so until they are able to catch up to AMD level of latency masking.

Meteorlake has been delayed so long that the desktop had to have a refresh of a refresh(because Raptorlake itself is a refresh fitting between Alder and Meteor).

All the complex words you are using to explain yourself can be summarized by the following: Intel failed to meet expectations. CPUs are basically a black box to consumers. It doesn't matter what way they use to get there. Guinea Pigs have no option of being there. Buyers do.

When plans go out of whack there are many details that the team cannot execute as well and does not perform to expectations. We don't know what they had to scale back in order to meet the delayed schedule. These are the kinds of details that maybe we'll get to hear from an engineer in an interview ten years from now. Even in Meteorlake's presentation we see their goal was to absolutely minimize the performance impact. It's not difficult to guess they have missed some of their original goals.

In theory Foveros should be better than the approach AMD uses for example. Rest are determined by execution, execution, execution. Another thing that didn't work out in theory was AMD's laptop chips and battery life prior to Zen 2. The chipset was on-die yet the Intel laptops with off-die PCH had significantly better battery life.

We shouldn't conclude Meteorlake's troubles will exactly port over to Arrowlake.

 

[maddie]

Exactly. Yearly launches shouldn't surprise anyone. But after years of people repeatedly posting here that the 5 nodes in 4 years won't happen, it is nice to see that there are actually plans for it to happen.

Yep. Just redefine the meaning of a word and presto, what was impossible is not anymore. So current 21st century.