Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Exist50]

But for ARL, what could have potentially happened:

LNC started development late 2019 for Intel 7nm and TSMC 3nm. This should be ready ~ late 2020, early 2021.
Hence we see the mid-late 2023 ARL-P leaks on TSMC 3nm.
Intel realigns roadmaps and foundries internally around late 2020/ early 2021. Announced to the public in mid 2021.
LNC gets 'redefined', starts development of 20A for a 2024 launch around early 2021. TSMC delays also ensured that their original 2023 launch date is unrealistic.
The core is ready by early 2022. This follows Xeno's leak of LNC being design frozen early 2022 (maybe for the 20A variant?)
ARL with LNC on 20A comes late, late 2024 or 2025, with the TSMC 3nm variants coming out around half a year to a year earlier.

This could explain how GNR is able to change core design to LNC so relatively quickly after only ~1 year delay from original release date. LNC's Intel 7nm development could already have had a lot of work done.

However two counter points to this could be:
1) LNC was always planned on Intel 20A, since Intel also thought Intel 20A would be ready by 2023 all the way back in 2019
2) LNC wasn't planned for any internal Intel nodes until early 2021, and was only planned for TSMC since late 2019.

Something to note about GNR though is that half way through 2021 Intel were still claiming GNR would be on Intel 4. Assuming that Intel switched tack to Intel 3 as soon as possible 2H 2021, they would need the development of the CPU to start essentially as soon as they switched, with little to no time to develop a core design.
However if Intel were designing LNC for Intel 7nm/Intel 3 from the start, they already would have LNC ready for the server team...

Schedule would be a tight fit but I think it's possible. Only problem is believing Intel would have so many separate design teams working all at the same time.
Very excited to see if we get any more info in a week during Intel's q1 earnings call

So, here's the picture that's forming in my head. I'm going to assume the RWC-based GNR rumors are true for now. If that proves to be false, will need to throw a lot of this out.

So, Intel almost certainly envisioned GNR as Intel 4 + RWC, arriving somewhere around 2022-2023. But at that point, they were probably also expecting SPR to fall comfortably within 2021. So SPR delays dragged on, with a knock-on effect on GNR, plus GNR probably had some of its own problems, and someone saw the writing on the wall that GNR would more realistically be a 2024 product, late 2023 at best.

Now, one very key thing to keep in mind about Intel's (at least historical) project (mis)management is that they're incredibly prone to scope creep. SPR started life as 2 tiles, Willow Cove, and PCIe 4.0. We see how that ended up. So someone probably said, "Hey, the SoC as a whole might be behind schedule, but these other bits (say, a new core, new process, etc) should be ready, so why don't we just™ swap those out?" This probably coincides with Gelsinger's comment. It's even possible they planned for an Intel 3 + Lion Cove compute tile as a follow-on generation, and were thinking they could basically skip the original GNR.

But naturally, this line of thinking always proves to be much easier on paper than reality. At this point someone probably bothered to ask the engineering teams how bad it would be, and got a sobering answer. So this one-off Intel 3 RWC+ idea ended up being the compromise solution. Probably for the best, because at this point I'm highly suspicious of Lion Cove.

 

[coercitiv]

SPR started life as 2 tiles, Willow Cove, and PCIe 4.0.

Wow. That explains a lot.

 

[A///]

a product shipped is a product shipped is something I have always said. I've been at big and small companies where we've shipped a giant steaming turd of a sku even with severe regressions because it's a product that shipped and didn't sit languishing in the labs like a sangria drunk broad at the english speaking section of a villa in mallorca.

 

[mikk]

MLID says they are testing 128-512MB L4 cache size for MTL at the moment.

 

[mikk]

Meteor Lake-S ES1 is sampling right now to OEMs, it's coming.

https://twitter.com/x/status/1649566200358215680

 

[Exist50]

MLID says they are testing 128-512MB L4 cache size for MTL at the moment.

Don't bet on it...

 

[A///]

Meteor Lake-S ES1 is sampling right now to OEMs, it's coming.

https://twitter.com/x/status/1649566200358215680

???????????????????????????

 

[mikk]

Don't bet on it...

The cache size or L4 in general?

???????????????????????????

My twitter link doesn't work, it's invisible. Forum software seems to be buggy. Try this embedded link.

Any idea how long it usually takes from ES1 sampling to shipping retails samples on desktop CPUs?

 

[Geddagod]

The cache size or L4 in general?




My twitter link doesn't work, it's invisible. Forum software seems to be buggy. Try this embedded link.

Any idea how long it usually takes from ES1 sampling to shipping retails samples on desktop CPUs?

Around a year

 

[moinmoin]

My twitter link doesn't work, it's invisible. Forum software seems to be buggy.

You’re unable to view this Tweet because this account owner limits who can view their Tweets.

Twitter user seems to be private. You'd need to make a screenshot.

 

[A///]

The cache size or L4 in general?




My twitter link doesn't work, it's invisible. Forum software seems to be buggy. Try this embedded link.

Any idea how long it usually takes from ES1 sampling to shipping retails samples on desktop CPUs?

????????????????????????

the account is private, all i see is replies

 

[Exist50]

The cache size or L4 in general?

The existence of commercial ADM SKUs for Meteor Lake.

 

[A///]

adm in this context is what Intel ADvanced Memory?

 

[Exist50]

adm in this context is what Intel ADvanced Memory?

Adamantium

 

[A///]

Adamantium

don't make me arrange kocicak to visit you.

 

[Geddagod]

the account is private, all i see is replies

unfortunate. It's basically what Mikk said tho, MTL-S ES sampling, and EMR ES2 sampling

The existence of commercial ADM SKUs for Meteor Lake.

IIRC the first leaks for ADM were from Jim at adored TV about ARL? MTL does seem a bit ambitious, esp with all the new technologies already being packed into it.
I also believe Intel already claimed that the base tile would be passive, idk if having cache on it would still make it passive... not familiar with the terminology tbh.

Adamantium

Intel's codenames get geekier by the day

 

[A///]

Intel's codenames get geekier by the day

He was serious with that? I thought he was being a smartass. I've been on a marvel film kick for a while and this was fresh in my mind.

 

[moinmoin]

He was serious with that?

Early Platform Hardening Technology For Slimmer And Faster Boot Patent Application

U.S. Patent Application 20210081538 for Early Platform Hardening Technology For Slimmer And Faster Boot

uspto.report

Money quote:
"Next generation client SoC architectures may introduce large on-package caches, which will allow novel usages. Access time for the L4 (e.g., "Adamantine" or "ADM") cache may be much less than the DRAM access time"

 

[Exist50]

IIRC the first leaks for ADM were from Jim at adored TV about ARL? MTL does seem a bit ambitious, esp with all the new technologies already being packed into it.
I also believe Intel already claimed that the base tile would be passive, idk if having cache on it would still make it passive... not familiar with the terminology tbh.

Afaik, MTL w/ ADM was cancelled long ago. They might be using it as kind of a test platform, but I don't think we'll see real products using it. ARL might be a different story, but not sure what the situation there is.

Either way, however, it would require a separate base die.

 

[msj10]

this diagram from the patent above seems to be MTL-M with 2 RWC + 8 CMT.
it shows the SOC die will have 2 Crestmont cores, and the base die can be passive or with ADM cache.

 

[BorisTheBlade82]

this diagram from the patent above seems to be MTL-M with 2 RWC + 8 CMT.
it shows the SOC die will have 2 Crestmont cores, and the base die can be passive or with ADM cache.

Good spot.
It is quite surprising, that these schematics seem to represent a real product. Is this just laziness in Intel's patent department? Usually everyone plays the Hide & Seek game.

 

[Henry swagger]

this diagram from the patent above seems to be MTL-M with 2 RWC + 8 CMT.
it shows the SOC die will have 2 Crestmont cores, and the base die can be passive or with ADM cache.

Wonder what the 2 crestmont cores in the soc will be doing ?🤔

 

[Geddagod]

Wonder what the 2 crestmont cores in the soc will be doing ?🤔

I'm guessing the idea is to simply be able to not use the core tile unless the user has to actually do something intensive. Should help battery life I'm guessing. It seems like a good way to counteract the inherent battery life loss of going chiplets for low power chips.

 

[BorisTheBlade82]

I'm guessing the idea is to simply be able to not use the core tile unless the user has to actually do something intensive. Should help battery life I'm guessing. It seems like a good way to counteract the inherent battery life loss of going chiplets for low power chips.

Yep, exactly. This has been rumoured for a long time already. Up until now it wasn't that clear what kind of core this would be and how many of them. 2 Atom cores do sound like a good idea for heavy idle (AV, Cloud Sync, Background updates etc.)

 

[coercitiv]

One of the power issues Intel had since many generations ago was keeping the entire CPU package at sleep when the Windows OS was idling. It's obviously not Intel specific, but back in the Haswell era for example they were the only option anyway.

For context, an idle well built and well configured Haswell-U laptop could hit 3-4W idle. The entire laptop. The setup was fragile though, with all kinds of things a user could do that would unknowingly prevent the CPU from entering Package C-States. I spend an entire afternoon trying to figure out why my notebook refused to idle properly, only to discover the culprit was a HDMI external connection (I was running the unit with an external monitor).

I've been moderately optimistic about hybrids in consumer laptops and a skeptic about their use in consumer desktop, but when it comes to including a few E cores in the SOC I would say I'm all in: it's a very good idea with lots of potential for power usage optimization.