Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[cannedlake240]

Ehh for one architecture sure but they are Jumping two architecture and one optimization.LNC has 14% ipc over RWC and cougar is 5% more and Panther is another 10-15% it is inline with modern architecture 🙂

Thats still not going to be anywhere near 40-50%, and 5% for cougar is probably too optimistic

 

[511]

Thats still not going to be anywhere near 40-50%, and 5% for cougar is probably too optimistic

40-50% may be not ve possible but 30-40% is definitely possible otherwise I don't think it will be competitive

 

[Kocicak]

They are offering a replacement CPU. I'm jumping ship. 14900K is too hard to cool and too prone to degradation for my tastes. I could just run at 4.5GHz and call it a day... but I'm an enthusiast! I can't go out like that.

I was telling you that 5.5 is too much. You will get a lot of perfomance from the new CPU, when you cap it from the beginning at 5 GHz.

If you want, jump ship the next year, when the truly updated AM5 platform is available.

 

[DrMrLordX]

Yeah unlike Granite, Diamond isn't stuck with a last gen core and process node. Apparently it has no SMT support which is a major downside. Core counts unknown

No SMT support? Where did you hear that?

 

[511]

Please don't say MLID

 

[cannedlake240]

No SMT support? Where did you hear that?

It comes up time to time in reddit threads. It's a rumor though, maybe the reason Forest line is being cancelled is because SMT is coming back to Panther cove-X

 

[naukkis]

10-15% at best should be the expectation for modern architectures. Memory and cache latency on GNR isn't great in HEX mode so if they can sort that out IPC uplift will be greater than Client. If latency can't be lowered at least get the capacity up through 3d stacking...

Intel Panther Cove will bring APX, which basically should give x86 similar performance possibilities than todays ARM. x86 is currently lacking about 50% IPC. If Intel doesn't target that with Panther Cove they are just losing their mind. And when they target that kind of high IPC they pretty much have no other option than drop SMT.

If they change their mind and re-introduce SMT they basically confirm that they have failed all their design targets and have gone to damage limitation mode.

 

[cannedlake240]

Intel Panther Cove will bring APX, which basically should give x86 similar performance possibilities than todays ARM. x86 is currently lacking about 50% IPC. If Intel doesn't target that with Panther Cove they are just losing their mind. And when they target that kind of high IPC they pretty much have no other option than drop SMT.

Nah anything more than 20% is extremely unlikely. ARM is 4.5Ghz max, way below the 5.7ghz of current x86 chips. They achieve basically the same perf, but the low clock speed approach is more efficient. Intel's experimental Royal core program that was recently canned allegedly targeted much higher IPC

 

[naukkis]

Nah anything more than 20% is extremely unlikely. ARM is 4.5Ghz max, way below the 5.7ghz of current x86 chips. They achieve basically the same perf, but the low clock speed approach is more efficient. Intel's experimental Royal core program that was recently canned allegedly targeted much higher IPC

So Intel bringing new instruction set architecture targeting performance and you except that they could not extract any performance out of it? Intel should gain that 20% for legacy x64 and have much more from native APX compared to legacy x64.

 

[cannedlake240]

So Intel bringing new instruction set architecture targeting performance and you except that they could not extract any performance out of it? Intel should gain that 20% for legacy x64 and have much more from native APX compared to legacy x64.

David Huang and Chester from CnC believe that perf improvement from APX will be negligible. Plus it apparently increases instruction length which will make the x86 decoding an even bigger headache

 

[SiliconFly]

.

 

[naukkis]

David Huang and Chester from CnC believe that perf improvement from APX will be negligible. Plus it apparently increases instruction length which will make the x86 decoding an even bigger headache

It does not cure everything on x86 - but doubling registers will outright reduce loads 10% and stores 20%. X86 with it stupid TSO ordering will greatly benefit from fewer stores. APX also makes possible to reduce branches from code. With those APX code should be equal to ARM at least with cpu designs that have mop cache to remove instruction decoding problems.

 

[dttprofessor]

Just waiting for the future of E core.

 

[dttprofessor]

Quite a few cloud use cases do not require high single-core performance. SRF is sufficient for these applications. No matter how strong the performance of CLW is, it will not cost the cloud more. SRF is sufficient.

 

[mikk]

No SMT support? Where did you hear that?

Exist50 told it, means it is most likely correct.

 

[Meteor Late]

Nah anything more than 20% is extremely unlikely. ARM is 4.5Ghz max, way below the 5.7ghz of current x86 chips. They achieve basically the same perf, but the low clock speed approach is more efficient. Intel's experimental Royal core program that was recently canned allegedly targeted much higher IPC

Eh 5.7GHz is on Desktop, on Laptop there is no 5.7GHz chip because it would consume a massive amount of power for single core. ARM limit is not 4.5GHz, I'm sure M4 can clock a bit higher, 200-300MHz more for sure, at what power cost though I don't know, probably very costly.

 

[Hulk]

I was telling you that 5.5 is too much. You will get a lot of perfomance from the new CPU, when you cap it from the beginning at 5 GHz.

If you want, jump ship the next year, when the truly updated AM5 platform is available.

You were correct.

What will the updated AM5 add?

 

[Kocicak]

What will the updated AM5 add?

I have no idea, but I believe it is impossible that AMD ran exactly the same platform for three consecutive years without updating it.

Now is a bad time for jumping ships, the next year you will be able to choose between a fixed CPU for LGA 1851 or even better CPUs for AM5 than are available today.

 

[dttprofessor]

Eh 5.7GHz is on Desktop, on Laptop there is no 5.7GHz chip because it would consume a massive amount of power for single core. ARM limit is not 4.5GHz, I'm sure M4 can clock a bit higher, 200-300MHz more for sure, at what power cost though I don't know, probably very costly.

maybe core 285hx（not ultra）5.7g

 

[AcrosTinus]

Well I'll be getting a warranty replacement on my 3rd Raptor CPU shortly. Running on auto "Intel safe" BIOS options with updated Intel microcode BIOS and max clock capped at 5.5GHz. Getting lock ups in Topaz Photo AI. Contacted them and they said check CPU stability Photo AI hits the CPU hard. I said, "Impossible, I'm 100% stable."

Just for kicks I backed max clock down to 4.5GHz and the issues with Photo AI are resolved.

Checked with Intel and based on S/N and batch number they said my CPU is "defective" and will send a new one.

Now the question do I use it or just bail and move to AMD? I want to bail as I'm tired of this. I just hate starting over with Windows from the ground up. But it's gotta happen sooner or later right? I think the writing is on the wall and I have to move on from Intel.

The only AMD mainstream that might be worth it is the 9950X with 3D-VCache to compensate the IO Die and RAM latency. Anything else is too weak, 9800x3D is nice but I am not buying 8 cores in 2024, not going to happen.

And Intel maybe in one of my dreams might implement a 3D cache equivalent, now that the tiles introduce latency and the L3 is quite weak, it might help or just introduce more latency.

I think Intel's strategy might be increasing L3 frequency like they did from Alder to Raptor, reintegrate the IMC into the compute die and introduce a LV4 cache to hide the D2D latency. I don't know how effective that approach might be but it is fair to say that Intel won't be taking any gaming crowns for nearly a decade maybe and frankly I don't care. I am on 4K with a 4070 Ti Super, these bottlenecks don't see me. I buy Intel for the stability *ahemmm* and their chipset, here AMD has to catch up as their chipset is only connected via a 4x lane. Z890 currently has more bandwidth but no real CPUs....

 

[Markfw]

The only AMD mainstream that might be worth it is the 9950X with 3D-VCache to compensate the IO Die and RAM latency. Anything else is too weak, 9800x3D is nice but I am not buying 8 cores in 2024, not going to happen.

And Intel maybe in one of my dreams might implement a 3D cache equivalent, now that the tiles introduce latency and the L3 is quite weak, it might help or just introduce more latency.

I think Intel's strategy might be increasing L3 frequency like they did from Alder to Raptor, reintegrate the IMC into the compute die and introduce a LV4 cache to hide the D2D latency. I don't know how effective that approach might be but it is fair to say that Intel won't be taking any gaming crowns for nearly a decade maybe and frankly I don't care. I am on 4K with a 4070 Ti Super, these bottlenecks don't see me. I buy Intel for the stability *ahemmm* and their chipset, here AMD has to catch up as their chipset is only connected via a 4x lane. Z890 currently has more bandwidth but no real CPUs....

Intel ? Stability ? you are in the wrong universe, see the Raptor lake instability threads

 

[AcrosTinus]

Intel ? Stability ? you are in the wrong universe, see the Raptor lake instability threads

It was a joke, "stability *ahemm*", thought it was on the nose

 

[AcrosTinus]

duplicate

 

[Markfw]

It was a joke, "stability *ahemm*", thought it was on the nose

SORRY !!!! I was commenting based on the rest. The 9800x3d if you are a gamer or 9950x for the test productive would have been my recommendation.

But sorry, this is an Intel thread. No more posts on this from me.

 

[511]

SORRY !!!! I was commenting based on the rest. The 9800x3d if you are a gamer or 9950x for the test productive would have been my recommendation.

Test productivity 😅
No matter how bad 14900K was it was not a regression like ARL was ARL would have been salvageable without the -ve gains it had