Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[DokiDoki]

So is Intel sandbagging LNCs IPC after all? They are claiming >20% ST performance over MTL on one of their Hot Chips Slides. Since LNLs clocks stayed basically the same, LNC IPC must be much better than 14% or am I missing something?

Unlikely though not impossible. When Cypress Cove backport was announced, it was claimed to have double-digit IPC. Final Rocket Lake had +19% IPC.

 

[Hitman928]

So is Intel sandbagging LNCs IPC after all? They are claiming >20% ST performance over MTL on one of their Hot Chips Slides. Since LNLs clocks stayed basically the same, LNC IPC must be much better than 14% or am I missing something?

The way I read it is at low power, LNL can give you 20+% ST performance thanks to clocking higher (MTL needs 30+ W to hit 5.1 GHz). If MTL is allowed to use more power and clock higher, LNL can give you the same ST performance at half the power. I could be wrong but that’s what I’m expecting.

 

[dullard]

So is Intel sandbagging LNCs IPC after all? They are claiming >20% ST performance over MTL on one of their Hot Chips Slides. Since LNLs clocks stayed basically the same, LNC IPC must be much better than 14% or am I missing something?

You need to be careful, the slide is for Single Threat performance, not Single Thread performance.

 

[Hitman928]

You need to be careful, the slide is for Single Threat performance, not Single Thread performance.

LNL oxidation issue confirmed! /s

(too soon?)

 

[cebri1]

Without knowing what is that they are comparing to make the 20% claim, it’s a useless statement.

 

[dullard]

The way I read it is at low power, LNL can give you 20+% ST performance thanks to clocking higher (MTL needs 30+ W to hit 5.1 GHz). If MTL is allowed to use more power and clock higher, LNL can give you the same ST performance at half the power. I could be wrong but that’s what I’m expecting.

That is pretty much what Intel's earlier slides showed. People focused on the +14% IPC gain at a single frequency, and totally ignored the other half of the slide. The other half of the slide was iso-power. It showed that:

• The performance gain is stronger than 14% at low power (low frequencies). See the red oval. 20% is >18%.
• The performance gain is less than 14% at high power (high frequencies). See the green oval.
• At the highest performance level (pushing the Meteor Lake to its highly inefficient limits), then Lion Cove can be half power for same performance (orange line). This is because you aren't pushing Lion Cove to its very maximum there, well outside the efficient range.

 

[511]

So is Intel sandbagging LNCs IPC after all? They are claiming >20% ST performance over MTL on one of their Hot Chips Slides. Since LNLs clocks stayed basically the same, LNC IPC must be much better than 14% or am I missing something?

In geekbench LNL gets approximately 19-20% my 185H scores 2450 and we have seen leaks of ~2900 so there claim based on Geekbench can be true

Alienware Alienware m16 R2 - Geekbench

Benchmark results for an Alienware Alienware m16 R2 with an Intel Core Ultra 9 185H processor.

browser.geekbench.com

Khadas MakerKit - Geekbench

Benchmark results for a Khadas MakerKit with an Intel Core Ultra 7 268V processor.

browser.geekbench.com

 

[DavidC1]

The way I read it is at low power, LNL can give you 20+% ST performance thanks to clocking higher (MTL needs 30+ W to hit 5.1 GHz).

At 17W it's possible. Meteorlake's Redwood Cove uses more than 20W on Single threaded Cinebench.

It's kinda shameful how much power it uses running 1 thread.

Looking at single-threaded power consumption in CineBench 2024, the Core Ultra 7 155H peaks at around 43 W before ramping down to a semi-consistent power range of between 27 and 30 W.

 

[Hitman928]

At 17W it's possible. Meteorlake's Redwood Cove uses more than 20W on Single threaded Cinebench.

It's kinda shameful how much power it uses running 1 thread.

That’s not even the top clocking part.

 

[SiliconFly]

.

 

[511]

Is it package power or IA power ? Cause the Package power on MTL is bad

 

[Hitman928]

Is it package power or IA power ? Cause the Package power on MTL is bad

Package. Just reducing the number of tiles probably saves a decent amount of ST power.

 

[Magio]

To be "fair" that's also the MTL-H part, which is meant to be able to stretch its legs quite a bit more than MTL-U (which I've seen little testing for, sadly) or LNL. Not that it delivers the kind of performance in ST that would justify that amount of leg stretching.

LNL seems like it handily outperforms it ST even when constrained to 17W package power (exact ST power consumption isn't known yet, of course).

 

[SiliconFly]

.

 

[H433x0n]

That is pretty much what Intel's earlier slides showed. People focused on the +14% IPC gain at a single frequency, and totally ignored the other half of the slide. The other half of the slide was iso-power. It showed that:

• The performance gain is stronger than 14% at low power (low frequencies). See the red oval. 20% is >18%.
• The performance gain is less than 14% at high power (high frequencies). See the green oval.
• At the highest performance level (pushing the Meteor Lake to its highly inefficient limits), then Lion Cove can be half power for same performance (orange line). This is because you aren't pushing Lion Cove to its very maximum there, well outside the efficient range.

View attachment 106334

I think they probably meant +20% peak ST performance, that’s how most would interpret it anyway.

Currently we’ve seen the 268V SKU achieve a score of ~2900-2915 in the GB6 1T test. We’ve yet to see GB6 scores from the 288V but that has a 5.1ghz fmax so it’s a reasonable assumption that it will net an additional ~+2% in the GB6 1T benchmark. This performance would have LNL net ~20% more performance over MTL 185H in the GB6 1T benchmark.

 

[dullard]

I think they probably meant +20% peak ST performance, that’s how most would interpret it anyway.

I interpret ">20% Single Threat performance" as +20% ST performance.

I also interpret that as >18% performance as shown in the graph. Different SKUs will have different peak powers.

 

[CouncilorIrissa]

I think they probably meant +20% peak ST performance, that’s how most would interpret it anyway.

Currently we’ve seen the 268V SKU achieve a score of ~2900-2915 in the GB6 1T test. We’ve yet to see GB6 scores from the 288V but that has a 5.1ghz fmax so it’s a reasonable assumption that it will net an additional ~+2% in the GB6 1T benchmark. This performance would have LNL net ~20% more performance over MTL 185H in the GB6 1T benchmark.

Could you link to the 2.9k 268V run? I only see the 288V doing 2.9.

edit: nvm found it by family number

 

[DavidC1]

Is it package power or IA power ? Cause the Package power on MTL is bad

IA cores just using 25W+ on ST would be horrible.

Intel says 1/2 power at same performance is under Cinebench ST.

 

[Doug S]

IA cores just using 25W+ on ST would be horrible.

Intel says 1/2 power at same performance is under Cinebench ST.

Horrible why, exactly?

In an ideal world you'd want a single core to be able to use as much power as it can usefully turn into increased performance. Up to the limit for the entire CPU. Because if you have a single threaded load and feeding one core 100 watts would allow it to clock higher and go 5-10% faster than it would at 10 watts (the curve gets steep so you aren't going to get a lot) wouldn't you want that as an option?

Now if it maxes out its performance at 25 watts and can't increase frequency while retaining reliability beyond that then sure there's no reason to feed it 100 watts. But you should at least want the option to push as much power into one core as it can usefully use, while remaining below the overall package power limits.

 

[DavidC1]

Because if you have a single threaded load and feeding one core 100 watts would allow it to clock higher and go 5-10% faster than it would at 10 watts (the curve gets steep so you aren't going to get a lot) wouldn't you want that as an option?

In a general sense you are not wrong, but relative to AMD it's bad, and compared to ARM it's indeed horrible. Apple does better while consuming a fraction of the power. 100W is I think 15x what Apple chips consume? It better be 3-5x fast at least, to justify battery dying in 3 years and making the whole thing useless, fans that need to run at 4000 RPM all the time, and temperatures to threaten the integrity of the chassis itself.

And if you think 25W ST is a good thing, oh boy do I have a bridge to sell you, because that's how you get laptops that can't be passive and run a fan all the time. Especially on Windows where in many cases you have a misbehaving process consuming significant amount of CPU cycles. For people like here they can shut it down or whatever, but for most it'll be a bad experience.

I had that just yesterday. I tried terminating it but it came back. So searching about it said I needed to restart the process from services.msc. Who wants to deal with that crap? There's many dozen processes I had to search for to see what it does, just so I can shut them down.

I hope Intel does a 180 degree mentality from what you suggested, because the market is seriously shifting to Smartphones, forever. It wasn't like this just 10 years ago. Now there are many popular apps that are afterthought on desktops. They might as well not exist.

 

[del42sa]

https://wccftech.com/intel-arrow-la...top-cpus-spotted-tackle-amd-strix-halo-apple/

• Five Tile Architecture (CPU,GPU,SOC,IO,L4)
• 6 Lion Cove P-Cores
• 8 Skymont E-Cores
• Up To 320 Xe-LPG EUs (20 Xe Cores)
• L4 Adamantine Cache
• Based on TSMC N3 Process Node

 

[511]

RWC is horrible at high Frequency also Intel 7 beats both 4nm class node 7840hs and ultra 155H

 

[511]

https://wccftech.com/intel-arrow-la...top-cpus-spotted-tackle-amd-strix-halo-apple/

• Five Tile Architecture (CPU,GPU,SOC,IO,L4)
• 6 Lion Cove P-Cores
• 8 Skymont E-Cores
• Up To 320 Xe-LPG EUs (20 Xe Cores)
• L4 Adamantine Cache
• Based on TSMC N3 Process Node

I hope it is Xe2 Xe1 is not that good for halo products

 

[Kepler_L2]

https://wccftech.com/intel-arrow-la...top-cpus-spotted-tackle-amd-strix-halo-apple/

• Five Tile Architecture (CPU,GPU,SOC,IO,L4)
• 6 Lion Cove P-Cores
• 8 Skymont E-Cores
• Up To 320 Xe-LPG EUs (20 Xe Cores)
• L4 Adamantine Cache
• Based on TSMC N3 Process Node

Cancelled long time ago.

 

[poke01]

https://wccftech.com/intel-arrow-la...top-cpus-spotted-tackle-amd-strix-halo-apple/

• Five Tile Architecture (CPU,GPU,SOC,IO,L4)
• 6 Lion Cove P-Cores
• 8 Skymont E-Cores
• Up To 320 Xe-LPG EUs (20 Xe Cores)
• L4 Adamantine Cache
• Based on TSMC N3 Process Node

This isn’t competitive at all with Strix Halo or M4 Max…