Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[AcrosTinus]

Thats sad. But I'm still hoping that it's somehow true!

I tried to analyze the image trying to find any ps edits, but the result was inconclusive. The (false) color bleed looks more like jpg compression artifact rather than alteration. Either the image is real or they've done an amazing pixel perfect job (which isn't difficult actually) or they might have faked it some other way. Hard to say.

View attachment 102250View attachment 102251

But what if it isn't fake? 😶

We will know soon enough but I think a score above 1K in CPU-Z is a given. Current CPUs with 5,7 to 5,8Ghz ST turbo do around 922 to 940. Irrespective of CPU-Z worth a 15% increase would put it around 1070 points if clocks don't regress.

Wasn't 20A with backside power(PowerVia) and gate all around(RibbonFet) transistors suppose to keep clock regression low or negate it ?

 

[SiliconFly]

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[KompuKare]

Oh yeah thats right. People saying CPU-Z is flawed benchmark. Well for AMD CPUs it seems to be but it seems more accurate for Intel CPUs? Though did not fully read them just scanned briefly so may have missed?

So am I not right or is that source not right?

There is another possibility about CPU-Z's benchmark:
The dev has been changing it for "reasons" supposedly just to align with actual code. However, what if those changes - which previously seem to favour Intel (at the expense of that other x86 who we will not mention in this Intel thread) - now no longer do?

A limited benchmark like CPU-Z (and the whole CPU-Z executable is only 4MB) can - like all benchmarks - only measure how good something is at running that benchmark, but what if the new Intel CPUs just don't get along with CPU-Z?

They may do quite well in other code. Or they may not. As always until hardware is released we can only speculate.

 

[cebri1]

Considering they are claiming 14% IPC uplift for Lion's Lunar Lake. I can see it reaching close to 16% for the Arrow Lake version. If there is indeed some clock regression, 10-12% increase while improving energy efficiency significantly will be a pretty good update over Raptor Lake.

 

[Wolverine2349]

Pat's words seem to indicate that 20A should clock higher. So, regression, even if it exists, should be marginal.

How is Intel 20A (the 6+8 die) compared to TSMC 3nm they are going to put the higher end 8+16 dies on? Are they the same or does one have an advantage?

 

[Elfear]

Pat's words seem to indicate that 20A should clock higher. So, regression, even if it exists, should be marginal.

I hope 20A knocks it out of the park but are we really expecting factory 6.2Ghz for ST workloads from Arrow Lake?

 

[SiliconFly]

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[AcrosTinus]

I hope 20A knocks it out of the park but are we really expecting factory 6.2Ghz for ST workloads from Arrow Lake?

I am hoping for 5,8Ghz, 6,2Ghz seems out of reach for a test node towards 18A but what do I know...

 

[SiliconFly]

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[Wolverine2349]

Many articles said N3B has slightly higher density (when comparing equivalent libraries), but 20A has slightly higher performance. But I think that for all practical purposes, there wouldn't be much of a difference. Also, the extra performance of 20A I'd directly attribute to BSPD.

Edit: Oopsie.. misread your question. My bad.

Is that primarily why 8 + 16 die is in N3B because it needs to be more dense to fit more cores 2 more P cores and 8 core e-cores?

Could Intel put 8 + 16 on their own 20A if the wanted or no?

 

[dullard]

Is that primarily why 8 + 16 die is in N3B because it needs to be more dense to fit more cores 2 more P cores and 8 core e-cores?

Could Intel put 8 + 16 on their own 20A if the wanted or no?

For the real answer, please take a look at this chart: https://forums.anandtech.com/thread...akes-discussion-threads.2606448/post-41180614 Notice how Intel doesn't have much 20A capacity in 2024 (green bar). They physically can't make large numbers of large tiles. Intel didn't buy enough equipment years ago to be able to do that. And the line to buy more equipment is years long. So Intel just physically cannot add capacity quickly.

Conspiracy answer: they are using TSMC, therefore Intel's 20A yield is too low to make any big chips. Of course, there is zero evidence for it, but you'll see that thought a lot.

 

[SiliconFly]

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[dullard]

Actually, the last part is true. Larger the die, lesser the yield. And that too it's not even linear. It's worse. The bigger the die, the yield gets more and more worse exponentially. Which in turn seriously hurts volume & increases cost.

For smaller dies, newer cutting edge nodes like 20A with moderate yields works really well. For larger dies, a more mature node with higher yield and larger capacity like N3B is the best fit.

In short, for 8+16, only N3B can meet the market demand (not practical/viable with newer nodes like 20A).

Yes, larger chips have lower yields. That is true for every company and every node. But that still says nothing about whether 20A yields are good or terrible or something in between. So your conclusion is still completely an unproven conspiracy until evidence emerges otherwise.

 

[Magio]

For the real answer, please take a look at this chart: https://forums.anandtech.com/thread...akes-discussion-threads.2606448/post-41180614 Notice how Intel doesn't have much 20A capacity in 2024 (green bar). They physically can't make large numbers of large tiles. Intel didn't buy enough equipment years ago to be able to do that. And the line to buy more equipment is years long. So Intel just physically cannot add capacity quickly.

Conspiracy answer: they are using TSMC, therefore Intel's 20A yield is too low to make any big chips. Of course, there is zero evidence for it, but you'll see that thought a lot.

What a colossal -redacted- up it was from Intel to pass up on EUV for so long, by the way. Now they're "overcompensating" by buying up all the early High NA EUV machines while TSMC is content to wait a while, and history will tell us if this will be a reversal of the DUV-EUV transition.

Profanity is not allowed in the tech forums.

Daveybrat
AT Moderator

 

[SiliconFly]

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[Henry swagger]

I am hoping for 5,8Ghz, 6,2Ghz seems out of reach for a test node towards 18A but what do I know...

lets wait for leaks.. intel is very secretive with what node arrow lake s will use

 

[deasd]

LNL supply would be very limited until next year:

https://twitter.com/x/status/1808386960471498945

EEP might means 'exclusive' or 'preemptive', only few top vendors have privilege and get on LNL supply earlier.

 

[coercitiv]

LNL supply would be very limited until next year:

EEP might means 'exclusive' or 'preemptive', only few top vendors have privilege and get on LNL supply earlier.

This would explain the behavior of the LG executive who complained about LNL availability.

 

[mikk]

Is this even a surprise? It was the same with Meteor Lake-H when it launched, first EEP models came out and then 2 or 3 months later non EEP models appeared. Almost all the big OEMs had 1 or 2 EEP models in the first few weeks after launch. It's better than what AMD does because it's usually Asus exclusive for the first 1-3 months after launch. Intel EEP is more than just Asus.

 

[FlameTail]

Lunar Lake
8 core Xe2 GPU
8 MB GPU L2 cache
8 MB SLC
LPDDR5X-8533 + 128 bit = 136 GB/s

Panther Lake
12 core Xe3 GPU

Panther Lake has a significantly beefed up GPU. How are they going to feed it?

Supposedly it's going to stick to LPDDR5X, and not upgrade to LPDDR6.

 

[DavidC1]

Lunar Lake
8 core Xe2 GPU
8 MB GPU L2 cache
8 MB SLC
LPDDR5X-8533 + 128 bit = 136 GB/s

Panther Lake
12 core Xe3 GPU

Panther Lake has a significantly beefed up GPU. How are they going to feed it?

Supposedly it's going to stick to LPDDR5X, and not upgrade to LPDDR6.

Improved architecture, that's how. Xe2 on LNL not only has doubled L2 cache but Fast Clear for lower bandwidth requirements(should be on both small ones such as instructions and large ones like textures).

Let's look at the history:
Icelake has support for LPDDR4x-3733

XeLP = 2x the performance
XeLPG on Meteorlake = 2x the performance
Xe2 on LNL = 1.5x the performance.

6x the performance with 2.3x the memory bandwidth. How did that work you might ask?

Pat mentioned during Intel Accelerated that they've pulled-in both 20A & 18A. That gives the nodes even less time than they need. 20A yields are not gonna be spectacular during debut. Hence, only smaller dies now.

Still the delusion regarding 20A. Why would such an AWESOMESAUCE node only be in 6+8 and only in desktop? Because it's not that good. You can also see how Intel 3 is quite a bit better than Intel 4 too. Conversely, Intel 4 product is just not that good. They are fast iterating to catch up and exceed competitors. That's the sole purpose of Intel 4 and 20A. Stepping stones.

"Hey Intel 4 and 20A isn't meeting expectations"
"No problem, the real ones are Intel 3 and 18A"

Intel only pulled in 18A not 20A. 20A was always 2024 H1 production. 18A went from 2025 H1 to 2024 H2.

 

[DavidC1]

A brand new node with all new cutting edge technologies like GAAFET & BSPD is not something any foundry is gonna master is a short span. Like all foundries, Intel too needs time to increase yield.

Who cares about high level specs? AMD had copper on 0.18u process but Intel's aluminum 0.18u demolished it. It was not even close. The drive current advantage was over 25%. Intel had their 0.18u specs in public. AMD had it hidden in some near obscure document. Because there was nothing to be proud of.

What about Samsung with endless iterations and high level leadership like GAA, but being atrocious in reality? TSMC is so ahead that the similar labeled node is almost a generation better, while also yielding far better.

You cannot have a F1 car with a 600 hp V16 alone. You need the chassis to be aerodynamic, the wheels to be large and smooth, the vehicle be very light, etc, etc.

I am hoping for 5,8Ghz, 6,2Ghz seems out of reach for a test node towards 18A but what do I know...

It was 5.7GHz on the leak. Intel 7 chips are overdue iterations of the 10nm process. You can perfect what you are doing you know? Polish it? The frequencies the desktop chips are running are beyond only process.

Same damn thing was said of 14nm vs 10nm, with people saying 10nm would go past 14nm, but it took years to do so.

 

[FlameTail]

It was 5.7GHz on the leak. Intel 7 chips are overdue iterations of the 10nm process. You can perfect what you are doing you know? Polish it? The frequencies the desktop chips are running are beyond only process.

Same damn thing was said of 14nm vs 10nm, with people saying 10nm would go past 14nm, but it took years to do so

They have refined and optimised 10nm so much, it's as if blood has been squeezes out of a stone.

 

[DavidC1]

They have refined and optimised 10nm so much, it's as if blood has been squeezes out of a stone.

Yea you need the new process to be power and area efficient. It was 14nm delays that put power increase substantial too. But clocks need to go down, not up.*

Back in the Pentium 4 days process itself was a game changer. It was around 90nm when it started to really slow down.

Now they need 10x the changes to get 0.7x the effect of the Golden Age of process.

*I repeated over and over again that modern clocks are basically only possible due to heatsinks being the size and weight of literal bricks, or common water cooling.

The cooling today is pseudo-exotic, and if you had such setups back 20 years ago, you could reach 5GHz clocks too.

 

[dullard]

A brand new node with all new cutting edge technologies like GAAFET & BSPD is not something any foundry is gonna master is a short span. Like all foundries, Intel too needs time to increase yield.

Valid points, but they still are insufficient for your conclusion. Until there is actual yield information (unlikely to get actual numbers but we can estimate eventually), you only have an unproven conclusion. Counterpoints: (1) smaller tiles have higher yields than doing it all large and monolithic, (2) Intel isn't doing that yield-killing quad patterning now that there is some EUV. Which wins out? Your points or the counterpoints? Without data, we can't make conclusions.