Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[jpiniero]

I wonder what's preventing Intel from expanding their capacity.

Intel needs their 90% server market share back.

 

[SiliconFly]

.

 

[SiliconFly]

.

 

[Aapje]

Yes, we're supposed to believe Intel will have capacity and manufacturing volume to do a vast amount of SKUs in the next 1- 2 years. But suddenly they'll lack it for NVL🤔.

Or perhaps i18A doesn't bring "unquestioned leadership".

AFAIK they never claimed that they would ship most, but just that their process would be the best...eventually.

@jur

Keep in mind that ASML isn't exactly a supermarket where you go in and the machines are lined up on the shelf for you to take home.

Even installing and dialing in these machines is a very lengthy process.

 

[dullard]

I wonder what's preventing Intel from expanding their capacity. Is there some other bottleneck besides EUV tools? They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool. This seems very irrational decision. Wouldn't it make much more sense to ramp 18A as fast as possible,

1) There is one and only one EUV supplier, with a massive backlog of orders. https://www.tomshardware.com/news/a...-hits-record-backlog-exceeds-dollar38-billion
2) There has been a massive chip demand boom. Covid shortages, crypto, and now AI. This makes the backlog for equipment even larger.
3) Intel didn't buy enough EUV machines and then didn't get in line for the machines early enough. Intel had bad management that made bad decisions. They totally missed the ball for this chip demand boom.

Combine the three and Intel is bottlenecked. There is no possible way to ramp 18A much faster without the equipment to do so.

 

[Hulk]

Intel with 18A in one hand behind their back and Intel 7 in the other hand saying, "Don't look at that look at THIS!"

 

[jpiniero]

2) There has been a massive chip demand boom. Covid shortages, crypto, and now AI. This makes the backlog for equipment even larger.

Not really, not anymore. The AI stuff is all packaging limited. Even N5, TSMC is in the process of retooling some of it for N3 and friends.

Intel doesn't have much capacity because they were hedging on whether to spin off the fabs... and whether they can actually afford to continue without putting the company at risk.

 

[H433x0n]

Read it. Interesting. Since you're so confident, what makes you think TSMC N2 differs a lot from Intel's "lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node"?

Where do you get 30-36nm pitches? And what feature?

 

[Hans Gruber]

Not really, not anymore. The AI stuff is all packaging limited. Even N5, TSMC is in the process of retooling some of it for N3 and friends.

Intel doesn't have much capacity because they were hedging on whether to spin off the fabs... and whether they can actually afford to continue without putting the company at risk.

The technology bill passed by Biden provides tens of billions to Intel and other companies to build and expand their fabs. Even TSMC got several billion for their Arizona operations.

 

[Hulk]

The technology bill passed by Biden provides tens of billions to Intel and other companies to build and expand their fabs. Even TSMC got several billion for their Arizona operations.

Hey, it's just money. Print away.

 

[poke01]

Thoughts on skymont?

 

[FlameTail]

Thoughts on skymont?

 

[DrMrLordX]

They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool.

To add to what others have said, keep in mind that Intel has abandoned plans to make 20a and/or 18a High NA EUV processes. The acquisition of advanced equipment has no bearing on their processes through the entirety of 2025.

 

[Doug S]

Where do you get 30-36nm pitches? And what feature?

Pitches have been misleading for a long time and are becoming even more misleading. Intel is increasing its pitch from 30 to 36nm with 18A because BSPDN/PowerVia allows a larger M0 pitch without compromising density which helps in multiple ways.

 

[H433x0n]

Pitches have been misleading for a long time and are becoming even more misleading. Intel is increasing its pitch from 30 to 36nm with 18A because BSPDN/PowerVia allows a larger M0 pitch without compromising density which helps in multiple ways.

What's the source for that? As far as I know there's nothing public on the features of 18A.

 

[SiliconFly]

.

 

[Aapje]

What's the source for that? As far as I know there's nothing public on the features of 18A.

Intel put out a slide:

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

 

[Ghostsonplanets]

Thoughts on skymont?

Should be a really good core. Kepler recently said that SKT has around SNC/Z3 performance. So you're basically getting an extra 5950X, alongside 8 Lion Cores, if you buy Core Ultra 9 2990K.

Should help ARL be a MT monster. On LNL, it will act more as a LPE core because it will lack L3 cache and is "off-ring" (iirc).

 

[tamz_msc]

SKT has around SNC/Z3 performance

Gracemont in Alder Lake already is ~95% of the per-clock integer performance of Cypress Cove. In Raptor Lake, it should surpass the PPC of Cypress Cove. Skymont should at minimum be Golden Cove level of PPC.

All this is based on the SPECint_rate 2017 1T numbers from past Anandtech reviews.

 

[mikk]

It's not clear if they refer to performance from IPC and clock speed combined. If it's IPC then I would agree SNC level isn't great when Gracemont already was basically on par with Skylake, at least on integer workloads. And seems like the Skymont cluster in Lunar Lake is quite a bit bigger now compared to Lion Cove big core.

https://twitter.com/x/status/1778860445853491346

 

[SolidQ]

Some news

https://twitter.com/x/status/1779161220807045335

 

[tamz_msc]

Some news

https://twitter.com/x/status/1779161220807045335

iTLB entries are the exact same as Golden Cove.
2M/4M doesn't refer to L2/L3 size.

 

[H433x0n]

Intel put out a slide:

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

That’s for Intel 4, not 18A.

 

[Thibsie]

It's fake. Huge Intel fanboy that doesn't know anything and he's usually all the time around tech twitter trying to get leaks.

Anyway, you can spot on that it's fake due to him claiming CPU tile and SoC tile are separated tiles fabricated on different nodes. While, from what we know, CPU and SoC tile are merged on PTL. The CPU core configuration is also straight out of MLID videos.

Yeah, that guy isn't worth the attention.

 

[mikk]

Yeah, that guy isn't worth the attention.

Too bad Ghostsonplanets is wrong with his tile prediction. Just because LNL integrate Soc into the compute tile doesn't mean Intel will do the same with their regular mobile lineup after Arrow Lake. Why should they do this if they are 18A volume limited. Panther Lake is not a MX chip, it's UPH. There is no On-package memory either based on the Intel slide.