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Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

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T

Tigerick

Senior member
Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

Intel Raptor Lake UIntel Wildcat Lake 15WIntel Lunar LakeIntel Panther Lake 4+0+4
Launch DateQ1-2024Q2-2026Q3-2024Q1-2026
ModelIntel 150UIntel Core 7 360Core Ultra 7 268VCore Ultra 7 365
Dies2223
NodeIntel 7 + ?Intel 18-A + TSMC N6TSMC N3B + N6Intel 18-A + Intel 3 + TSMC N6
CPU2 P-core + 8 E-cores2 P-core + 4 LP E-cores4 P-core + 4 LP E-cores4 P-core + 4 LP E-cores
Threads12688
Max Clock5.4 GHz4.8 GHz5 GHz4.8 GHz
L3 Cache12 MB6 MB12 MB12 MB
TDP15 - 55 W15 - 35 W17 - 37 W25 - 55 W
Memory128-bit LPDDR5-520064-bit LPDDR5x-7467128-bit LPDDR5x-8533128-bit LPDDR5x-7467
Size96 GB48 GB32 GB128 GB
Bandwidth83 GB/s60 GB/s136 GB/s120 GB/s
GPUIntel GraphicsIntel GraphicsArc 140VIntel Graphics
RTNoNoYESYES
EU / Xe96 EU2 Xe8 Xe4 Xe
Max Clock1.3 GHz2.6 GHz2 GHz2.5 GHz
NPUGNA 3.017 TOPS48 TOPS49 TOPS






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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



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Last edited:
Ghostsonplanets said:
Yes, we're supposed to believe Intel will have capacity and manufacturing volume to do a vast amount of SKUs in the next 1- 2 years. But suddenly they'll lack it for NVL🤔.

Or perhaps i18A doesn't bring "unquestioned leadership".
Click to expand...

AFAIK they never claimed that they would ship most, but just that their process would be the best...eventually.

@jur

Keep in mind that ASML isn't exactly a supermarket where you go in and the machines are lined up on the shelf for you to take home.

Even installing and dialing in these machines is a very lengthy process.
 
jur said:
I wonder what's preventing Intel from expanding their capacity. Is there some other bottleneck besides EUV tools? They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool. This seems very irrational decision. Wouldn't it make much more sense to ramp 18A as fast as possible,
Click to expand...
1) There is one and only one EUV supplier, with a massive backlog of orders. https://www.tomshardware.com/news/a...-hits-record-backlog-exceeds-dollar38-billion
2) There has been a massive chip demand boom. Covid shortages, crypto, and now AI. This makes the backlog for equipment even larger.
3) Intel didn't buy enough EUV machines and then didn't get in line for the machines early enough. Intel had bad management that made bad decisions. They totally missed the ball for this chip demand boom.

Combine the three and Intel is bottlenecked. There is no possible way to ramp 18A much faster without the equipment to do so.
 
dullard said:
2) There has been a massive chip demand boom. Covid shortages, crypto, and now AI. This makes the backlog for equipment even larger.
Click to expand...

Not really, not anymore. The AI stuff is all packaging limited. Even N5, TSMC is in the process of retooling some of it for N3 and friends.

Intel doesn't have much capacity because they were hedging on whether to spin off the fabs... and whether they can actually afford to continue without putting the company at risk.
 
jpiniero said:
Not really, not anymore. The AI stuff is all packaging limited. Even N5, TSMC is in the process of retooling some of it for N3 and friends.

Intel doesn't have much capacity because they were hedging on whether to spin off the fabs... and whether they can actually afford to continue without putting the company at risk.
Click to expand...
The technology bill passed by Biden provides tens of billions to Intel and other companies to build and expand their fabs. Even TSMC got several billion for their Arizona operations.
 
jur said:
They ordered 6 high NA tools and each of these costs twice as much as latest low NA tool.
Click to expand...

To add to what others have said, keep in mind that Intel has abandoned plans to make 20a and/or 18a High NA EUV processes. The acquisition of advanced equipment has no bearing on their processes through the entirety of 2025.
 
Doug S said:
Pitches have been misleading for a long time and are becoming even more misleading. Intel is increasing its pitch from 30 to 36nm with 18A because BSPDN/PowerVia allows a larger M0 pitch without compromising density which helps in multiple ways.
Click to expand...
What's the source for that? As far as I know there's nothing public on the features of 18A.
 
poke01 said:
Thoughts on skymont?
Click to expand...
Should be a really good core. Kepler recently said that SKT has around SNC/Z3 performance. So you're basically getting an extra 5950X, alongside 8 Lion Cores, if you buy Core Ultra 9 2990K.

Should help ARL be a MT monster. On LNL, it will act more as a LPE core because it will lack L3 cache and is "off-ring" (iirc).
 
Ghostsonplanets said:
SKT has around SNC/Z3 performance
Click to expand...
Gracemont in Alder Lake already is ~95% of the per-clock integer performance of Cypress Cove. In Raptor Lake, it should surpass the PPC of Cypress Cove. Skymont should at minimum be Golden Cove level of PPC.

All this is based on the SPECint_rate 2017 1T numbers from past Anandtech reviews.
 
It's not clear if they refer to performance from IPC and clock speed combined. If it's IPC then I would agree SNC level isn't great when Gracemont already was basically on par with Skylake, at least on integer workloads. And seems like the Skymont cluster in Lunar Lake is quite a bit bigger now compared to Lion Cove big core.


https://twitter.com/x/status/1778860445853491346
 
Ghostsonplanets said:
It's fake. Huge Intel fanboy that doesn't know anything and he's usually all the time around tech twitter trying to get leaks.

Anyway, you can spot on that it's fake due to him claiming CPU tile and SoC tile are separated tiles fabricated on different nodes. While, from what we know, CPU and SoC tile are merged on PTL. The CPU core configuration is also straight out of MLID videos.
Click to expand...
Yeah, that guy isn't worth the attention.
 
Thibsie said:
Yeah, that guy isn't worth the attention.
Click to expand...


Too bad Ghostsonplanets is wrong with his tile prediction. Just because LNL integrate Soc into the compute tile doesn't mean Intel will do the same with their regular mobile lineup after Arrow Lake. Why should they do this if they are 18A volume limited. Panther Lake is not a MX chip, it's UPH. There is no On-package memory either based on the Intel slide.
 
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