Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[AMDK11]

Why not? They already have two different variants of Lion Cove for their client platforms. Lion Cove for Arrow Lake & Lion Cove+ for Lunar Lake. One more for server isn't that difficult considering Lion Cove is a grounds up new architecture (kick started by Jim Keller himself).

LionCove+ will be something like RaptorCove compared to GoldenCove or RedwoodCove. Nothing more.

Intel already has two micro architectures to deal with, Cove and Mont, and removing AVX512 means redesigning the P core, which no one will see. I'm sure about this.

 

[SiliconFly]

LionCove+ will be something like RaptorCove compared to GoldenCove or RedwoodCove. Nothing more.

Intel already has two micro architectures to deal with, Cove and Mont, and removing AVX512 means redesigning the P core, which no one will see. I'm sure about this.

I remember reading some articles that had mixed views about the AVX-512 die area during the Linus Torvalds AVX controversy. Many claimed that AVX-512 instructions take up significant die space (as much as 25% per core) due to it's complex logic. While a few others claimed that AVX-512 support doesn't take up significant space in the total die area.

If the former is true, then having AVX-512 support in the die and then fused off is a complete waste of expensive silicon and adds up to cost significantly (25% is a ton of money). Having two separate designs makes a lot of sense considering LNC is new.

 

[AMDK11]

I remember reading some articles that had mixed views about the AVX-512 die area during the Linus Torvalds AVX controversy. Many claimed that AVX-512 instructions take up significant die space (as much as 25% per core) due to it's complex logic. While a few others claimed that AVX-512 support doesn't take up significant space in the total die area.

If the former is true, then having AVX-512 support in the die and then fused off is a complete waste of expensive silicon and adds up to cost significantly (25% is a ton of money). Having two separate designs makes a lot of sense considering LNC is new.

AVX512 is included in the logic of the entire x86 core, e.g. in Front-end and Load/Store. Alternatively, LionCove will get 2x 512 in the basic micro architecture instead of 1x 512, but 100% there will be no separate project for the P core without physically AVX512.

Moreover, the AVX512 logic in LionCove, even though it will be disabled, will be expanded

 

[adroc_thurston]

But still gonna be light years ahead of Zen5 I presume.

Man this is funny.

 

[SiliconFly]

..even though it will be disabled, will be expanded

Leading the way for AVX10? 🧐

 

[SiliconFly]

Man this is funny.

But nothing compared to yours.

 

[itsmydamnation]

Ya. Agree. Nothing special. But still gonna be light years ahead of Zen5 I presume.

why , they have way more "stuff" then Zen4 and are basically equal, i would call Zen4 tiny stuff compared to GC.
Zen5 adds alot more "stuff" , so even if Zen5 doesn't get smarter it will still likely be significantly more performance per "stuff". so in this scenario Intel is going to need alot more stuff^2.

 

[SiliconFly]

why , they have way more "stuff" then Zen4 and are basically equal, i would call Zen4 tiny stuff compared to GC.
Zen5 adds alot more "stuff" , so even if Zen5 doesn't get smarter it will still likely be significantly more performance per "stuff". so in this scenario Intel is going to need alot more stuff^2.

Thats kinda interesting actually. We should start measuring cpus using performance per "stuff".

 

[igor_kavinski]

Thats kinda interesting actually. We should start measuring cpus using performance per "stuff".

Once done benchmarking, put the CPUs in water and measure their "density" using the Archimedes Principle

 

[mikk]

Intel even in panther lake is behind in AI performance. So PTL will have 50 TOPS for the NPU meanwhile Qualcomms NPU in the X elite already has 45 TOPS already in 2024.

So PTL launches in late 2025. Intel is behind in every metric. CPU, GPU and even NPU.

How do you get 50 TOPS for Panther Lake? The rumoured NPU Tops for Lunar Lake is roughly 40 or slightly above 40 TOPS. Panther Lake according to Intel brings a 2x improvement over Lunar Lake which then makes it to something between 80-85. So how do you get 50 Tops? There is no X Elite device in the market right, it might become available in Summer right? It has a couple of months at best before Lunar Lake arrives. Same question regarding CPU and GPU, what is your source of your claims? Do you have a link to your claims? What are the performance projections of Panther Lake and Qualcomm (whatever they have in late 2025)?

 

[AMDK11]

Leading the way for AVX10? 🧐

If the P and e cores in ArrowLake are AVX10 compatible then 512bit will be activated for LionCove. I think so.

 

[igor_kavinski]

If the P and e cores in ArrowLake are AVX10 compatible then 512bit will be activated for LionCove. I think so.

I really hope so. Sucks really bad for AVX-512 adoption among software developers since Intel is the volume leader and no one will risk investing time and effort in an optimization that most users won't be able to use. I hate under utilization of something nice especially when it can bring potentially significant performance gain.

 

[adroc_thurston]

How do you get 50 TOPS for Panther Lake?

that's SOC tops, includes the iGP and CPU too.

 

[Philste]

Intel even in panther lake is behind in AI performance. So PTL will have 50 TOPS for the NPU meanwhile Qualcomms NPU in the X elite already has 45 TOPS already in 2024.

Isn't X Elite 45 TOPS INT4, whereas the Intel and AMD measurements are INT8? x86 CPUs are not as far behind as one would think, apart from the fact that it isn't that important after all.

 

[poke01]

Isn't X Elite 45 TOPS INT4, whereas the Intel and AMD measurements are INT8? x86 CPUs are not as far behind as one would think, apart from the fact that it isn't that important after all.

nope the X elite tops are INT8.

 

[mikk]

that's SOC tops, includes the iGP and CPU too.

Are you telling me Panther Lake will be slower than Lunar Lake? LNL should exceed 50 Tops all combined.

 

[Philste]

Are you telling me Panther Lake will be slower than Lunar Lake? LNL should exceed 50 Tops all combined.

More: Bionic Squash claims the following:Due to XMX coming back in ARLs iGPU the combined TOPs will rise to 70+ even with the 10-13 TOPs NPU.

 

[poke01]

More: Bionic Squash claims the following:View attachment 95438Due to XMX coming back in ARLs iGPU the combined TOPs will rise to 70+ even with the 10-13 TOPs NPU.

Who ever has the most TOPS wins 2024?

 

[maddie]

Who ever has the most TOPS wins 2024?

The new CPU battle cry. TOP that.

 

[SiliconFly]

...Due to XMX coming back in ARLs iGPU the combined TOPs will rise to 70+ even with the 10-13 TOPs NPU.

Those XMX units will primarily be used for gaming/xess upscaling by many. Other than that, all these NPU, TOPS, etc are not much of an use for most. It's mostly a fad as of now I feel. May pickup in the future if some real mass-market use cases pop up.

 

[mikk]

More: Bionic Squash claims the following:View attachment 95438Due to XMX coming back in ARLs iGPU the combined TOPs will rise to 70+ even with the 10-13 TOPs NPU.

85 Tops from iGPU and NPU combined, with CPU may be closer to 100 Tops wich is in line to Intels 3x over Meteor Lake claim.

About Panther Lake there is a BGA2540-PTL-UPH Interposer Intel offers, does it mean it isn't just a Lunar Lake-M successor.

The BGA2540-PTL-UPH Interposer adapts the Gen5 VR Test Tool to Arrow Lake HX series platforms that use the BGA2540 Panther Lake CPU package.

Design and Validation Tools, Tool Store - Review, Marketing Platform - Designer Resources

designintools.intel.com

 

[igor_kavinski]

All Intel peasant cores may suffer slight performance loss: https://www.tomshardware.com/pc-com...ips-not-hugely-affected-by-rfds-vulnerability

 

[poke01]

All Intel peasant cores may suffer slight performance loss: https://www.tomshardware.com/pc-com...ips-not-hugely-affected-by-rfds-vulnerability

Not if you have an i5 12400 😛

 

[SiliconFly]

...peasant cores may suffer slight performance loss...

Think thats performance loss? Think again!

The Empire Strikes Back... M3 MacBook Air loses close to half its performance in clamshell mode.

Apple’s M3 MacBook Air Loses Nearly 50 Percent Of Its Performance When Used In Clamshell Mode, Reveals Stress Test

In clamshell mode, the M3 MacBook Air can support more monitors, but a recent test shows that it loses a ton of performance in the process

wccftech.com

 

[uzzi38]

More: Bionic Squash claims the following:View attachment 95438Due to XMX coming back in ARLs iGPU the combined TOPs will rise to 70+ even with the 10-13 TOPs NPU.

Yeah XMX has to come back, because MS's TOPs requirements are only getting larger as time goes on. It's a lot more area efficient (AKA cheaper to produce and for the end consumer later) to use XMX than it is to slap on an even _bigger_ NPU, even if the NPU would be more power efficient.

LNL being a premium part is going to beat the 50 TOPs numbers by slapping on a phat NPU, as it makes sense to do so given the low TDP range it's designed for. So both power consumption demands and premium status means Intel have a good reason to go the NPU route. But ARL-H doesn't get that chance - needs to be cheaper, and it also can go to much higher TDPs, so XMX is a good enough solution.