Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[Henry swagger]

The lesser known impact of Sierra Forest is that it comes merely 1H after they say Intel 3 is in production, when for Intel 4 it took a year.

I think there's also a significance in saying 18A is 1H ahead of 20A. 20A product comes in H2 2024 with Arrowlake. Logically, 18A product is Clearwater Forest in H1 2025. Cutting the gap alludes to improved design execution.

288 cores of Skymont that's on par with Golden Cove in average(Int and FP), on 18A in 2025 will truly mark "undisputed leadership").

Nah amd is still ahead in data center.. intel will have unquestioned leadership as pat said with diamond rapids

 

[SiliconFly]

You might be reading too much into the exact timings for released chips. Intel had too little fab capability. For quite a while Intel did not have enough lithography equipment for large scale production on Intel 4 and Fab 9 for its Foveros packaging just came on line. https://www.anandtech.com/show/21246/intels-foveros-advanced-packaging-fab-9-starts-operations Both meant that Intel could only build small amounts of Meteor Lake chips.

Basically Intel had Intel 4 ready a long time before it was released, but not enough capacity to actually build it in volume. Simply improving fab capacity is a long ways away from proving that there is "improved design execution".

I still think Intel 4 & 3 don't have enough volume per se. It appears their next big high volume node is not even 20A, but actually 18A. Thats probably one of the reasons they mentioned they're betting everything on 18A.

 

[SiliconFly]

Nah amd is still ahead in data center.. intel will have unquestioned leadership as pat said with diamond rapids

Intel might have a marginal lead in client with their upcoming products. But, AMD's upcoming cores appear to be better suited for data center than Intel's upcoming cores. Diamond rapids may not match Zen5 series in overall server performance and/or efficiency. AMD's dense cores are particularly very impressive.

 

[igor_kavinski]

AMD claims Ryzen smashes Intel's Meteor Lake in AI benchmarks — up to 79% faster at half the power consumption

Local AI processing in Llama 2 and Mistral Instruct 7B seem much faster on AMD.

www.tomshardware.com

In the demo we watched, an AMD exec said that AVX512 and VNNI acceleration built into the Zen 4 CPU cores were behind the winning results you see in the charts. That's interesting, as we expected to be told about the more powerful NPU in the Phoenix vs Meteor Lake processors.

Oh dear God! Pat, just admit defeat and enable AVX-512 on MTL.

 

[Markfw]

AMD claims Ryzen smashes Intel's Meteor Lake in AI benchmarks — up to 79% faster at half the power consumption

Local AI processing in Llama 2 and Mistral Instruct 7B seem much faster on AMD.

www.tomshardware.com

Oh dear God! Pat, just admit defeat and enable AVX-512 on MTL.

I don't think the transistors are in it to enable it, right ? While googling on the subject, I found this from tomshardware.com

Next-gen Intel Arrow Lake-S CPU spotted with 24-threads and no AVX-512 functionality​

 

[eek2121]

Am I reading this correctly?
Let's look at 2GHz.
4 Gracemont cores requires about 3000J
4 Golden Cove cores requires about 3750J
4 Skylake Cores requires about 4200J

I knew that Gracemont was area efficient but I did not know that below about 3.2GHz it is more power efficient than Golden Cove.

This chart brings some economic realities of CPU manufacturing to light. First of all, if you want incredible MT efficiency just throw a huge amount Gracemont clusters at 1.4GHz at the task. For ST 6 or 8 Golden Coves will do the job. Problem is of course that would be a huge and expensive die!

Performance/Efficiency/Cost

Pick two. You can have performance and efficiency but at higher cost. Or low cost and high efficiency but you'll also have low performance. Or you can have low cost and high performance and low cost (Raptor Lake).

The reason I put Zen 4 above Raptor Lake is because it does much better than Raptor Lake at hitting high performance, high efficiency, and low cost.

Cost is due to die size, which is derived from the process and density. I state this because you can make a design which balances performance/density/efficiency, or you can optimize for one or two while sacrificing the others. Intel clearly goes all in on performance, whereas AMD appears to balance things out. (See my response to the below post)

Intel might have a marginal lead in client with their upcoming products. But, AMD's upcoming cores appear to be better suited for data center than Intel's upcoming cores. Diamond rapids may not match Zen5 series in overall server performance and/or efficiency. AMD's dense cores are particularly very impressive.

Intel’s issue is that their big cores aren’t as well designed as Zen because they spent years optimizing for absolute performance. The atom cores were originally designed for phones and tablets so they favor efficiency and die area. Because of this, Intel has been able to gradually move towards a good balance of perf/efficiency/area.

AMD drops performance in exchange for area/cost for the Zen4c cores. This leaves Intel in a situation where they need a faster Atom or a more efficient Cove core, but they have neither. However that is about to change.

IMO they really need a clean slate design

 

[igor_kavinski]

I don't think the transistors are in it to enable it, right ?

Slight chance it may have it if the compute die is shared with their server one. With Arrow Lake, maybe they will debut AVX10 or something?

 

[eek2121]

Slight chance it may have it if the compute die is shared with their server one. With Arrow Lake, maybe they will debut AVX10 or something?

They might add some of the instructions to the NPU.

 

[AMDK11]

I don't think the transistors are in it to enable it, right ? While googling on the subject, I found this from tomshardware.com

Next-gen Intel Arrow Lake-S CPU spotted with 24-threads and no AVX-512 functionality​

'm 99% sure that in RedwoodCove and LionCove the AVX512 physically occupies the transistors in the core as it does in SunnyCove and GoldenCove. AVX512 is part of the core microarchitecture. There's really no reason to think it will be any different since Xeon and Core(i/Ultra) processors use the same P-cores.

The only difference is that since AlderLake the AVX512 is inactive.

 

[controlflow]

AMD claims Ryzen smashes Intel's Meteor Lake in AI benchmarks — up to 79% faster at half the power consumption

Local AI processing in Llama 2 and Mistral Instruct 7B seem much faster on AMD.

www.tomshardware.com

Oh dear God! Pat, just admit defeat and enable AVX-512 on MTL.

The AMD solution used its CPU, GPU and NPU. Does LM studio even support the Intel NPU or GPU?

 

[igor_kavinski]

I have this fantasy that Intel Thread Director is firmware based so once they figure out how to make it recognize AVX-512 code and prevent it from scheduling it on the E-cores, they will retroactively enable AVX-512 on all consumer Golden Cove cores. Just waiting for that one fine day...

 

[igor_kavinski]

Does LM studio even support the Intel NPU or GPU?

We will find out when Intel defends MTL with their own blogpost!

 

[dullard]

The AMD solution used its CPU, GPU and NPU. Does LM studio even support the Intel NPU or GPU?

According to Tom's Hardware, no, it doesn't use Intel's NPU or GPU. So this is a comparison of just Intel's CPU vs. AMD's CPU + GPU + NPU.

AMD fires back at Nvidia and details how to run a local AI chatbot on Radeon and Ryzen — recommends using a third-party app

It's not complicated and also works with Intel CPUs and Nvidia GPUs.

www.tomshardware.com

"You could try LM Studio instead, though it doesn't appear to have Intel GPU or NPU support yet, so it would just use your CPU."

Intel's NPU is quite weak in Meteor Lake, so it wouldn't help much. But the GPU might help. The NPU is supposed to be 3x better in Lunar Lake and then 5x better than Meteor Lake in Panther Lake. By then the NPU should be better than the GPU.

 

[Markfw]

'm 99% sure that in RedwoodCove and LionCove the AVX512 physically occupies the transistors in the core as it does in SunnyCove and GoldenCove. AVX512 is part of the core microarchitecture. There's really no reason to think it will be any different since Xeon and Core(i/Ultra) processors use the same P-cores.

The only difference is that since AlderLake the AVX512 is inactive.

alder was disabled, and raptorlake. But MTL does not even have it, and from the link, not arrowlake either. and since Intel is monolithic, I don't think the cores are identical.

 

[poke01]

According to Tom's Hardware, no, it doesn't use Intel's NPU or GPU. So this is a comparison of just Intel's CPU vs. AMD's CPU + GPU + NPU.

AMD fires back at Nvidia and details how to run a local AI chatbot on Radeon and Ryzen — recommends using a third-party app

It's not complicated and also works with Intel CPUs and Nvidia GPUs.

www.tomshardware.com

"You could try LM Studio instead, though it doesn't appear to have Intel GPU or NPU support yet, so it would just use your CPU."

Intel's NPU is quite weak in Meteor Lake, so it wouldn't help much. But the GPU might help. The NPU is supposed to be 3x better in Lunar Lake and then 5x better than Meteor Lake in Panther Lake. By then the NPU should be better than the GPU.

Intel even in panther lake is behind in AI performance. So PTL will have 50 TOPS for the NPU meanwhile Qualcomms NPU in the X elite already has 45 TOPS already in 2024.

So PTL launches in late 2025. Intel is behind in every metric. CPU, GPU and even NPU.

 

[AMDK11]

alder was disabled, and raptorlake. But MTL does not even have it, and from the link, not arrowlake either. and since Intel is monolithic, I don't think the cores are identical.

In AlderLake this was disabled via bios/microcode, but in Raptorlake it was disabled at an even more advanced level. GoldenCove and RaptorCove contain physically the same FPU. Moreover, in RedwoodCove the FPU is also identical because the basic microarchitecture in RedwoodCove AVX512 exists the same as in RaptorCove.

I'm sure AVX512 exists physically in LionCove because Intel won't develop two different P-Core microarchitectures.

This is not about deleting the block with AVX512 registers. AVX512 is included in almost all P-core logic.

Removing the P-Core logic means a completely new core design and a separate design for Xeon.

 

[Markfw]

In AlderLake this was disabled via bios/microcode, but in Raptorlake it was disabled at an even more advanced level. GoldenCove and RaptorCove contain physically the same FPU. Moreover, in RedwoodCove the FPU is also identical because the basic microarchitecture in RedwoodCove AVX512 exists the same as in RaptorCove.

I'm sure AVX512 exists physically in LionCove because Intel won't develop two different P-Core microarchitectures.

Well, I am not sure of any of it. When Intel comes out with the chips, lets look at benchmarks, then talk. Yes, Raptorcove is physically disconnected for avx-512.

 

[Khato]

The AMD solution used its CPU, GPU and NPU. Does LM studio even support the Intel NPU or GPU?

You're giving AMD's software enabling capabilities too much credit. The article specifically states:

As a reminder of the properties of the latest Ryzen chips that align themselves to local AI acceleration, AMD says that three kinds of cores can be used in concert: NPU, RDNA 3 GPU, and Zen 4 CPU. In the demo we watched, an AMD exec said that AVX512 and VNNI acceleration built into the Zen 4 CPU cores were behind the winning results you see in the charts.

So basically this is AMD saying that they have AVX-512 VNNI enabled on their consumer processors while Intel doesn't. It's apparently far easier to design a hardware NPU than it is to get software to make use of it.

 

[AMDK11]

Well, I am not sure of any of it. When Intel comes out with the chips, lets look at benchmarks, then talk. Yes, Raptorcove is physically disconnected for avx-512.

In RaptorLake and RedwoodCove, AVX512 logic transistors physically exist and that is certain. In LionCove, I am confident that AVX512 logic will also appear. In the basic microarchitecture there will be 1x512bit, and for Xeon with additional logic, which will give a total of 2x512bit. I don't expect anything else. In LionCove, the only thing that can be for ArrowLake is that AVX512 is disabled at the hardware level, but it will still exist physically.

You will remember my words.

 

[Markfw]

In RaptorLake and RedwoodCove, AVX512 logic transistors physically exist and that is certain. In LionCove, I am confident that AVX512 logic will also appear. In the basic microarchitecture there will be 1x512bit, and for Xeon with additional logic, which will give a total of 2x512bit. I don't expect anything else. In LionCove, the only thing that can be for ArrowLake is that AVX512 is disabled at the hardware level, but it will still exist physically.

You will remember my words.

I won't remember, but I will discuss things when each new CPU comes out.

 

[SiliconFly]

...a completely new core design and a separate design for Xeon.

Why not? They already have two different variants of Lion Cove for their client platforms. Lion Cove for Arrow Lake & Lion Cove+ for Lunar Lake. One more for server isn't that difficult considering Lion Cove is a grounds up new architecture (kick started by Jim Keller himself). Not an evolution of Redwood Cove.

 

[adroc_thurston]

considering Lion Cove is a grounds up new architecture

It's more stuff.

 

[SiliconFly]

It's more stuff.

Ya. Lots of stuff.

 

[adroc_thurston]

Lots of stuff.

No. Just more stuff.
Like a new dcache level and more PRF capacity.
Nothing special at all.

 

[SiliconFly]

No. Just more stuff.
Like a new dcache level and more PRF capacity.
Nothing special at all.

Ya. Agree. Nothing special. But still gonna be light years ahead of Zen5 I presume.