Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[H433x0n]

Okay, great. Now explain why you think Intel 4 is actually high yield. Given how many critical products (especially Ponte Vecchio) had to be pulled off Intel 4, my guess is that Intel 4 has a high defect rate.

it doesn’t, this chart is normalized to defect density per 100mm2. If an intel product is scrapped or delayed at this point it’s probably more attributable to the design side instead of the fabs.

 

[DrMrLordX]

it doesn’t, this chart is normalized to defect density per 100mm2. If an intel product is scrapped or delayed at this point it’s probably more attributable to the design side instead of the fabs.

That chart has no numbers, and it compares Intel 4 in its current state to 10SF. 10SF was only used for relatively-small Tiger Lake mobile dice.

 

[SpudLobby]

U can say crap without getting the ban hammer? Today I learned

M3 is ~150 ye.
LNL cache structure:
LNC+ with increased L1 compared to LNC, 3MB of private L2 (split into 0.5MB of fast L2 and 2.5MB of slower L2), ? on L3, SLC

Looks at SPR

Rumored to be slightly better LNC. Think RWC>RPC. Same node, ARL should have N3 variants, as would LNL. I wonder if LNL might end up being on N3E vs ARL prob being on N3B, or if LNL development started too early to potentially make that switch.

Alchemist+. Doubled the L2, XMX, not bad.

LNL is exclusively N3 (B or E) no? No 18A. ARL has both though rumored

 

[SpudLobby]

oh interesting — that chart is normalized to defects/100mm^2?

I thought they were going off an average of their products at the time and good dice, basically cheating it.

That’s actually extremely encouraging for Intel 4 and Intel now with EUV.

Parametric yield is a separate question but seems more likely to be mediocre to just okay for now.

 

[SpudLobby]

That chart has no numbers, and it compares Intel 4 in its current state to 10SF. 10SF was only used for relatively-small Tiger Lake mobile dice.

It says normalized to “% yield for 100mm^2 of silicon”. So while Intel 4’s is smaller presumably they extrapolate outwards for the yields were they 100mm^2, and downwards for the others. That’s still great yield here. The reason they’re still using other nodes from TSMC was because of capacity, timelines and de risking in case things didn’t go so well. It makes sense. If 20A and 18A go as well as Intel 4 and ideally better on parametric yield, Intel may be alright

Edit: I agree yield wasn’t ideal at that point with 10SF but they also list Skylake 14NM there. Further Tiger Lake had some larger dice with 8 core SKUs. For where they are with Intel 4 this is a step ahead of previous yields. Ideally Intel 3 and 18A/20A will be another step ahead.

 

[jpiniero]

it doesn’t, this chart is normalized to defect density per 100mm2. If an intel product is scrapped or delayed at this point it’s probably more attributable to the design side instead of the fabs.

Says "yield", not defect density. Two different things. Being a chiplet that's only cores allows much better salvaging.

Devil's in the details of course.

 

[Thunder 57]

View attachment 91720
What is this....

Another embarassment is what it is. There are no Ultra 9 processors out yet. Hell, finding any MTL CPU is a challenge at this point. If their Ultra 5 can barely do "AI effects" on video calls, what can their lower end CPU's manage?

 

[DrMrLordX]

Further Tiger Lake had some larger dice with 8 core SKUs.

True, but those were never produced in large volume, and we have no idea how much trouble Intel had getting those to yield properly versus the more-common 4c dice.

Something seems off about the entire comparison. Maybe what @jpiniero is saying is closer to the truth, that they're including successful die salvaging in their yield figures to fluff up the numbers a bit. I have no confidence that Ponte Vecchio in particular was moved off of Intel 4 for reasons of "capacity and de-risking", though I can completely understand them doing that due to timelines, e.g. Intel 4 just wasn't ready and Intel had contracts to fulfill.

 

[LightningZ71]

The 8 core tiger lake dice also had an iGPU with 1/3 the number of EU. The resulting product wasn't massively larger than the original 4 core dice.

 

[H433x0n]

True, but those were never produced in large volume, and we have no idea how much trouble Intel had getting those to yield properly versus the more-common 4c dice.

Something seems off about the entire comparison. Maybe what @jpiniero is saying is closer to the truth, that they're including successful die salvaging in their yield figures to fluff up the numbers a bit. I have no confidence that Ponte Vecchio in particular was moved off of Intel 4 for reasons of "capacity and de-risking", though I can completely understand them doing that due to timelines, e.g. Intel 4 just wasn't ready and Intel had contracts to fulfill.

It's listed as better than Skylake, which was the 2nd generation of 14nm. It wouldn't surprise me if it's yielding better than Intel 7 is *right now*. There's 60% less masks for the first 5 metal layers, that's a huge deal. That's 60% less opportunities to introduce a defect at the most critical layers of silicon. Watch this video, specifically at the 12:40 mark.

 

[SiliconFly]

Okay, great. Now explain why you think Intel 4 is actually high yield. Given how many critical products (especially Ponte Vecchio) had to be pulled off Intel 4, my guess is that Intel 4 has a high defect rate.

I believe it's because of low volume due to less availability of EUV tools (and not yield). Intel themselves mentioned once that Intel 4 yield is extremely good (due to EUV).

 

[SiliconFly]

LNL is exclusively N3 (B or E) no? No 18A. ARL has both though rumored

Looks like LNL is N3B exclusive as Intel currently has no N3E designs in the works afaik.

ARL is supposed to be 20A exclusive. And the ARL on N3B rumor I think is unsubstantiated and hence should be taken with a bucket of salt.

 

[SiliconFly]

Another embarassment is what it is. There are no Ultra 9 processors out yet. Hell, finding any MTL CPU is a challenge at this point. If their Ultra 5 can barely do "AI effects" on video calls, what can their lower end CPU's manage?

Audio effects

 

[SpudLobby]

Looks like LNL is N3B exclusive as Intel currently has no N3E designs in the works afaik.

ARL is supposed to be 20A exclusive. And the ARL on 20A rumor I think is unsubstantiated and hence should be taken with a bucket of salt.

What? You contradict yourself. Is it 20A exclusive or not?

My bet is the N3B guys are right and it’s both but we will see

 

[SiliconFly]

What? You contradict yourself. Is it 20A exclusive or not?

My bet is the N3B guys are right and it’s both but we will see

Sorry. Typo. Fixed it. Also, ARL on N3B is doubtful.

 

[DrMrLordX]

Super 7? I haven't heard Intel 7 referred to as that. For a moment I thought it was the late 90's again!

Lol yeah apparently it's a thing. The variant used for Raptor Lake and presumably Emerald Rapids is called Super 7 by some folks. I can't find a decent link since most searches for Super 7 return hits for late variants of Socket 7. Bleh. Anyway bottom line is, the Intel 7 used in the latest Intel 7 products is supposed to be better than what they used on Alder Lake and Sapphire Rapids.

It's listed as better than Skylake, which was the 2nd generation of 14nm. It wouldn't surprise me if it's yielding better than Intel 7 is *right now*. There's 60% less masks for the first 5 metal layers, that's a huge deal. That's 60% less opportunities to introduce a defect at the most critical layers of silicon. Watch this video, specifically at the 12:40 mark.

I can see that, but again . . . IF that's true, Intel would have (or should have) leveraged Intel 4 for a number of products instead of just Meteor Lake. Things they didn't release on Intel 4 (announced or otherwise):

Ponte Vecchio
Loihi 2 (might have gone to some beta testers but that's it)
Any desktop CPU
Any server CPU

Intel didn't even release an Intel 4 variant of their Ridge CPUs. Instead they farmed out the node to Ericcson for their RAN SoC. Which strikes me as really odd.

 

[mikk]

Looks like LNL is N3B exclusive as Intel currently has no N3E designs in the works afaik.

ARL is supposed to be 20A exclusive. And the ARL on N3B rumor I think is unsubstantiated and hence should be taken with a bucket of salt.

ARL is supposed to use 20A+N3(B) depending on the version. This is what every reputable insider says and even Intel in their leadership roadmap mentioned 20A and N3. Most likely ARL-S 8+16 uses N3B.

 

[SiliconFly]

ARL is supposed to use 20A+N3(B) depending on the version. This is what every reputable insider says...

Hope the reputable insider isn't MLID. Sometimes, his version of the truth is way off from actual truth.

...Intel in their leadership roadmap mentioned 20A and N3. Most likely ARL-S 8+16 uses N3B.

No they didn't. Thats the whole point of this long discussion in the last two or three days. Kindly go thru the thread. Almost all the source material used by reputable sources have been discussed in detail in this thread and most of the the reputable sources themselves have referred to that same confusing Intel slide and some have mentioned it saying that it's their interpretation. Thats what this entire discussion is all about. Kindly go thru this thread and the actual source material included for further clarification.

 

[mikk]

No they didn't. Thats the whole point of this long discussion in the last two or three days. Kindly go thru the thread. Almost all the source material used by reputable sources have been discussed in detail in this thread and most of the the reputable sources themselves have referred to that same confusing Intel slide and some have mentioned it saying that it's their interpretation. Thats what this entire discussion is all about. Kindly go thru this thread and the actual source material included for further clarification.

They said it will be using 20A and N3. What is unclear on this for you?

 

[SiliconFly]

They said it will be using 20A and N3. What is unclear on this for you?

What about this Intel slide? What is unclear on this for you?

Like I said, thats the whole point of this entire discussion. I don't think we should cherry pick. We've considered all the known leaks & sources and have been trying to eliminate all improbabilities. And trying to come to a solid conclusion. Perhaps you should first go thru the thread for the bigger picture before jumping into any conclusion.

 

[mikk]

What about this Intel slide? What is unclear on this for you?

20A+external, how is this a contradiction for you? Because they didn't specify the exact external node?

 

[Tigerick]

What about this Intel slide? What is unclear on this for you?

Like I said, thats the whole point of this entire discussion. I don't think we should cherry pick. We've considered all the known leaks & sources and have been trying to eliminate all improbabilities. And trying to come to a solid conclusion. Perhaps you should first go thru the thread for the bigger picture before jumping into any conclusion.

You are the one who cherry pick. The slide clearly stated ARL is using both 20A and External N3B. Lunar Lake is using N3B since Intel Next is not 18A and will be used for future CPU...

If you really check the power efficiency of MTL, you should know MTL tGPU is appraised for power efficiency but not tCPU. At least you should check why Ultra 9 has to increase TDP to 45W and why U series is still using 2P and 4 Xe graphics. All these indicate Intel 4 process is not up to TSMC standard. That's why Intel has to opt to use N3B for most next gen CPU...Don't believe everything Intel's claim, it seems Qualcomm has totally baited out on IFS cause Intel process suck at PPA...

 

[SiliconFly]

You are the one who cherry pick. The slide clearly stated ARL is using both 20A and External N3B. Lunar Lake is using N3B since Intel Next is not 18A and will be used for future CPU...

It also clearly says LNL is Intel Next. What is next after 20A for Intel if not 18A? And also LNL is not on Intel node anymore, it's clearly N3B alone. Thats one contradiction.

...Don't believe everything Intel's claim...

Thats why this discussion.

 

[SiliconFly]

20A+external, how is this a contradiction for you? Because they didn't specify the exact external node?

It also says MTL is Intel 4+external, thats a contradiction as MTL is not on TSMC. It also says LNL is 18A+external, which is also a contradiction (LNL is N3B exclusive, not Intel). Like I said, thats the whole point of the discussion. Kindly go thru the thread. All these things have already been discussed.

 

[SpudLobby]

What. MTL is on TSMC, but for the GPU and SoC tile. In the same way, Arrow Lake’s external reference at minimum is about the GPU, but it just as easily could mean we will see ARL on TSMC exclusively (besides Foveros) as well as some ARL skus with 20A + N3B.

What you wouldn’t expect is N3B *only* for the whole part and no skus with a 20A tile.

But at any rate, Silicon Fly isn’t thinking through this.

LNL also says “LNL + Beyond” not “Lunar Lake”. It’s ambiguous. Beyond can reference Panther Lake etc on 18A. LNL, FWIW, was never even on 18A.