Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing Raptor Lake-U. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q1 2026.

		Intel Raptor Lake U	Intel Wildcat Lake 15W?	Intel Lunar Lake		Intel Panther Lake 4+0+4
Launch Date		Q1-2024	Q2-2026	Q3-2024		Q1-2026
Model		Intel 150U	Intel Core 7	Core Ultra 7 268V		Core Ultra 7 365
Dies		2	2	2		3
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		Intel 18-A + Intel 3 + TSMC N6
CPU		2 P-core + 8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		4 P-core + 4 LP E-cores
Threads		12	6	8		8
Max Clock		5.4 GHz	?	5 GHz		4.8 GHz
L3 Cache		12 MB		12 MB		12 MB
TDP		15 - 55 W	15 W ?	17 - 37 W		25 - 55 W
Memory		128-bit LPDDR5-5200	64-bit LPDDR5	128-bit LPDDR5x-8533		128-bit LPDDR5x-7467
Size		96 GB		32 GB		128 GB
Bandwidth				136 GB/s
GPU		Intel Graphics	Intel Graphics	Arc 140V		Intel Graphics
RT		No	No	YES		YES
EU / Xe		96 EU	2 Xe	8 Xe		4 Xe
Max Clock		1.3 GHz	?	2 GHz		2.5 GHz
NPU		GNA 3.0	18 TOPS	48 TOPS		49 TOPS

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[FlameTail]

So how big is the LNL dies all combined?

 

[SiliconFly]

I don't think we'll see any serious delays anymore... ...it's all about the people working on it.

More than the people, it's the process. It was one of Jim Keller's primary tasks. Now that MTL is out and the process is in place, future processors shouldn't experience any more serious delays as dependencies are minimal and each team works individually and faster. They save a ton of time in debugging and validation. One of the main reason they're able to work on both ARL & LNL at the same time.

 

[uzzi38]

So LNL basically has the same CPU cores as ARL, but on a better node (18A)?

That and Battlemage iGPU instead of Alchemist in ARL.

Uh, who said that LNL's on 18A?

 

[FlameTail]

Uh, who said that LNL's on 18A?

Mospbpdy

 

[SiliconFly]

Mospbpdy

LNL is N3B

Side note: Intel doesn't have any N3E products in 2024.

 

[eek2121]

It does if yields are too low on Intel 4 to produce a monolithic die of that size. Admittedly it makes more sense for a High NA EUV process with smaller reticle limits.

Intel’s yields on Intel 4 are said to be higher then Intel 7.

View attachment 91607
LNL gets shown off. Compute die, SOC die, and rumored dummy structural die.
Area efficiency doesn't look too great TBH. The compute die alone on N3 looks to be the same size as the M3 die.

Big cores + it combines GPU + CPU.

LNL is N3B

Side note: Intel doesn't have any N3E products in 2024.

*sigh* here we go again.

The package Intel showed off? The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

I have only found 1 single original source for the N3B rumors, and he cites “unnamed sources” which is code for “I might be making this up.”

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.

 

[trivik12]

We should get benchmark leaks in next few months if the systems are with OEM. There is no way intel can keep it under wraps. If course these early samples will not be at similar clockspeeds to retail but hopefully ipc numbers can be judged. If oneraichu is correct, LNC will be 8-wide core. So that would be close to Apple cores(which are 9-wide if I am not wrong). Question is would Intel would bump up cache numbers. Plus the most important thing is performance per watt. I dont think current chips lack in performance.

I dont think Lunar Lake can release this year if it uses 18A. That will go to volume production only late this year. It cannot release until mid next year. It could be 20A or N3.

 

[Hitman928]

Intel’s yields on Intel 4 are said to be higher then Intel 7.

Big cores + it combines GPU + CPU.


*sigh* here we go again.

The package Intel showed off? The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

I have only found 1 single original source for the N3B rumors, and he cites “unnamed sources” which is code for “I might be making this up.”

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.

Looks pretty legit to me? I think the current leaks point to the first and bulk of LNL being on N3B with a smaller volume being on 18a next year.

 

[SiliconFly]

Intel’s yields on Intel 4 are said to be higher then Intel 7.

Intel 4 may have higher yields than Intel 7. But Intel 7 is a high volume node. Tons of capacity. Intel 4 not so much cos it's a purpose built node for MTL's CPU tile.

*sigh* here we go again.

The package Intel showed off? The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

I have only found 1 single original source for the N3B rumors, and he cites “unnamed sources” which is code for “I might be making this up.”

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.

Maybe he was making it up. Even I has a hard time believing Intel will shift their CPU tile to TSMC. Feels wrong.

But after looking at this photo, it isn't clear anymore. LNL has a single CPU+GPU tile. Does that mean LNC+Battlemage are on a Intel node now? Or is it the other way around that both LNC+Battlemage are on TSMC? I thought Battlemage was a TSMC only design considering the upcoming Battlemage dGPU card is N3B. It's super expensive for amd, nvidia & also for Intel to have 2 different designs for the same gpu on 2 different nodes at the same time. I don't think it's even viable.

Also, 18A is at least 6 months behind 20A according to Intel themselves. Meaning, early 2025 volume ramp & time to market will be Q3 2025 at best. LNL is a Q4 2024 product. The timelines don't add up. LNL can't be on 18A. LNL on N3B makes sense (as Battlemage dGPU is N3B & LNC is node agnostic). LNL on 20A also makes some sense as LNC is already on 20A (due to ARL). But LNL on 18A, nah.

 

[DavidC1]

Lunarlake is TSMC N3B. I don't know why that's such a hard thing to believe. Intel 4 and 20A doesn't have full libraries for Lunarlake either. It also was in concept during a time when the confidence towards their process was very low.

Also, Meteorlake's battery life is so great Lenovo has introduced a laptop where the base portion is Meteorlake and Tablet portion is Snapdragon.

 

[Hitman928]

Also, Meteorlake's battery life is so great Lenovo has introduced a laptop where the base portion is Meteorlake and Tablet portion is Snapdragon.

What is this sorcery, lol, do you happen to have a link handy?

 

[adroc_thurston]

The package Intel showed off? The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

LNL is N3b.
It's also very huge for what it is.

 

[DavidC1]

Looks at SPR

This is what I meant when I said for short cycle products like semiconductors delays make it worse. It's what 3 years late now?

Surely you can't think current SPR is such an improvement over maybe original DMR plans?

@Hitman928 Feast on this glory.

Lenovo ThinkBook Plus Gen 5 Hybrid sticks Snapdragon 8+ Gen 1-powered tablet on top of an Intel Meteor Lake laptop

The ThinkBook Plus Gen 5 Hybrid is Lenovo's fresh take on a new type of 2-in-1. It consists of a laptop and a tablet, both of which can be used in unison or individually.

www.notebookcheck.net

 

[SiliconFly]

LNL is N3b.
It's also very huge for what it is.

Can't be very sure. All evidence points to N3B... but we still need some form of official confirmation or a proper source before it becomes a fact. Cos, CPU tile on TSMC is a big deal for Intel imho (I maybe wrong).

 

[DavidC1]

Can't be very sure. All evidence points to N3B... but we still need some form of official confirmation before it becomes a fact. Cos, CPU tile on TSMC is a big deal for Intel imho (I maybe wrong).

It is a big deal. They had to cause they screwed up. If it was on their own process they would have said it. You don't need them to be confirming to know what's going on. You can read between the lines so to speak, unless you are ChatGPT.

 

[Hitman928]

LNL is N3b.
It's also very huge for what it is.

Any idea why it's so big? Based on the leaked block diagram, it looks like the P-cores have L3 and then there is an additional 8mb of SLC which will take up some space but even still, it seems a bit big for a 4P+4E compute core. Are the iGPU and/or NPU taking up a ton of space?

 

[DavidC1]

All those who believe Lunarlake is Intel process are probably the same that still believe Kraznich got fired over sleeping with a subordinate, when Intel was hosting "private" parties for executives and systems partners after Intel Developer Forum was over.

Suure. Whatever makes you sleep at night.

 

[adroc_thurston]

but we still need some form of official confirmation

Slides posted are the official confirmation.

Any idea why it's so big? Based on the leaked block diagram, it looks like the P-cores have L3 and then there is an additional 8mb of SLC which will take up some space but even still, it seems a bit big for a 4P+4E compute core. Are the iGPU and/or NPU taking up a ton of space?

Well let's just say LNC is huge and bad.

 

[trivik12]

Laptops like MSI Prestige 16 already has good battery life with Meteor Lake.

LG Gram announced yesterday was talking about 24 hour battery life with IPS Screen !!!

 

[SiliconFly]

Well let's just say LNC is huge and bad.

Not at all. No one knows how performant LNC is gonna be. It can be a dud... or it might be out of the world.

 

[cebri1]

Lunarlake is TSMC N3B. I don't know why that's such a hard thing to believe. Intel 4 and 20A doesn't have full libraries for Lunarlake either. It also was in concept during a time when the confidence towards their process was very low.

Also, Meteorlake's battery life is so great Lenovo has introduced a laptop where the base portion is Meteorlake and Tablet portion is Snapdragon.

Actually is pretty good in most reviews but it's not a tablet chip.

 

[dullard]

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

You would sooner convince me that AMD is using IFS.

Is this the hill you are going to fight for? Evidence for your side: you think that is the way it would be. Heck, your own argument fails on its own merits (TSMC already is producing some E cores on Meteor Lake).

Evidence that Intel will use TSMC:
1) From Intel:
https://www.intel.com/content/www/u...technology-roadmaps-milestones.html#gs.2tquli

Lunar Lake and Beyond – Fueled by its IDM 2.0 strategy, Intel will be using both internal and external process nodes to deliver leadership products.

2) From Intel: https://download.intel.com/newsroom/2022/corporate/2022-Intel-Investor-Meeting-Client.pdf

Combine that with a 2024 Lunar Lake launch and 18A not launching until 2025 makes a pretty strong case for External.

3) Supposedly leaked from Intel: https://www.tomshardware.com/news/intel-lunar-lake-mx-to-use-tsmc-n3b


4) From Intel (Gelsinger): https://www.anandtech.com/show/1657...-on-intel-ip-blocks-for-foundry-cores-on-tsmc

Intel’s x86 Designs No Longer Limited to Intel on Intel: IP Blocks for Foundry, Cores on TSMC

5) From Intel (Gelsinger): https://www.tomshardware.com/news/intel-pat-gelsinger-clients-want-custom-x86-socs

We are going to make selective use of foundries. […] If I need to use a foundry to have a unique product or a halo product and certain portions, absolutely.

I could go on, but they are just variations of the above.

 

[Geddagod]

This is what I meant when I said for short cycle products like semiconductors delays make it worse. It's what 3 years late now?

I think it's 5? years late. Development started 2015 IIRC, if they expected development to take 3 years, that would be released in 2018, and SPR launched 2023.

Surely you can't think current SPR is such an improvement over maybe original DMR plans?

Idk what you mean by this, I'm sorry

 

[Geddagod]

The compute did was apparently made on Intel 18a (they also showed off a wafer full of them). Intel’s last public slide mentioning lunar lake also showed 18A.

Cap. Source?

Intel would look pretty foolish talking about process leadership and coming up with this elaborate plan, executing on it for years, and then turning around and saying “just kidding guys, IFS sucks, we are using TSMC”.

ARL is dual sourced. It uses 20A as well.
And server chips, aka the big "wow you can yield!" chips are on Intel nodes as well.

with a smaller volume being on 18a next year.

I don't think LNL will ever be on 18A, unless it's a LNL successor, but isn't that just PTL as well?

Intel 4 and 20A doesn't have full libraries for Lunarlake either.

Intel doesn't like fin depopulation. Undense, large cores with UHP and HP logic cells are their mojo. Last time they tried to buck that trend, it exploded in their faces.

Well let's just say LNC is huge and bad.

The LNC core complex looks to be around as big as a RWC core complex. I doubt a Zen 5 core complex is any smaller, unless they managed to get a really good shrink on the ringbus and L3 portions of the core complex, and even then...

Not at all. No one knows how performant LNC is gonna be. It can be a dud... or it might be out of the world.

With all the info so far, it looks bad. The only person saying its good is MLID.
Also idk why you have such a hard time believing this, but whatever.

 

[adroc_thurston]

No one knows how performant LNC is gonna be

ARL numbers are known lol.

The LNC core complex looks to be around as big as a RWC core complex.

Yeah on N3. That's the problem.

I doubt a Zen 5 core complex is any smaller, unless they managed to get a really good shrink on the ringbus and L3 portions of the core complex, and even then...

Z5 quad is considerably higher performance, while being N4p.

With all the info so far, it looks bad

At least Skymont is decent so there's that.