Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads

[Tigerick]

Wildcat Lake (WCL) Preliminary Specs

Intel Wildcat Lake (WCL) is upcoming mobile SoC replacing ADL-N. WCL consists of 2 tiles: compute tile and PCD tile. It is true single die consists of CPU, GPU and NPU that is fabbed by 18-A process. Last time I checked, PCD tile is fabbed by TSMC N6 process. They are connected through UCIe, not D2D; a first from Intel. Expecting launching in Q2/Computex 2026. In case people don't remember AlderLake-N, I have created a table below to compare the detail specs of ADL-N and WCL. Just for fun, I am throwing LNL and upcoming Mediatek D9500 SoC.

		Intel Alder Lake - N	Intel Wildcat Lake	Intel Lunar Lake		Mediatek D9500
Launch Date		Q1-2023	Q2-2026 ?	Q3-2024		Q3-2025
Model		Intel N300	?	Core Ultra 7 268V		Dimensity 9500 5G
Dies		2	2	2		1
Node		Intel 7 + ?	Intel 18-A + TSMC N6	TSMC N3B + N6		TSMC N3P
CPU		8 E-cores	2 P-core + 4 LP E-cores	4 P-core + 4 LP E-cores		C1 1+3+4
Threads		8	6	8		8
Max Clock		3.8 GHz	?	5 GHz
L3 Cache		6 MB	?	12 MB
TDP		7 W	Fanless ?	17 W		Fanless
Memory		64-bit LPDDR5-4800	64-bit LPDDR5-6800 ?	128-bit LPDDR5X-8533		64-bit LPDDR5X-10667
Size		16 GB	?	32 GB		24 GB ?
Bandwidth			~ 55 GB/s	136 GB/s		85.6 GB/s
GPU		UHD Graphics		Arc 140V		G1 Ultra
EU / Xe		32 EU	2 Xe	8 Xe		12
Max Clock		1.25 GHz		2 GHz
NPU		NA	18 TOPS	48 TOPS		100 TOPS ?

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

 

[igor_kavinski]

My hunch is on skymont team not Pat this time 🙂

They have enemies

 

[511]

They have enemies

I hope they get re orged or booted out cause the P core team after Haswell is a mess Skylake was a mess so many bugs and stuck on 14nm.

GLC was definitely an improvement though in every way shape and form.

 

[AcrosTinus]

I hope they get re orged or booted out cause the P core team after Haswell is a mess Skylake was a mess so many bugs and stuck on 14nm.

GLC was definitely an improvement though in every way shape and form.

Golden Cove, like Skylake, will be hard to overcome. Mark my words, for more than half a decade nothing will be substantially faster (excluding Apple, these people are doing something special: My Mac Mini M4 Pro, feels faster in day to day browsing, never expected that).

 

[511]

Golden Cove, like Skylake, will be hard to overcome. Mark my words, for more than half a decade nothing will be substantially faster (excluding Apple, these people are doing something special: My Mac Mini M4 Pro, feels faster in day to day browsing, never expected that).

Oh Apple has the most freedom in terms of designs they don't have to waste time for validation of supporting old code and don't have to deal with Complex Decoding of x86 this saves tons of time.
And they did not stagnate like Intel which is a good thing and their designs are the best rn.

 

[511]

PTL A0:

https://twitter.com/x/status/1896169661169062108

 

[511]

At least the CEO is capable

Intel Appoints Lip-Bu Tan as Chief Executive Officer

www.intc.com

 

[Hulk]

At least the CEO is capable

Intel Appoints Lip-Bu Tan as Chief Executive Officer

www.intc.com

As one of the commentors over at Toms wrote...

"So Intel has chosen death."

 

[QuickyDuck]

As one of the commentors over at Toms wrote...

"So Intel has chosen death."

Fabless intel could be revived like AMD

 

[511]

Fabless intel could be revived like AMD

No lol it won't Intel will be just another fabless without a big strategic advantage

 

[poke01]

Lip-Bu is good. He was also the chairperson at Nuvia. He knows his stuff

 

[DavidC1]

Oh Apple has the most freedom in terms of designs they don't have to waste time for validation of supporting old code and don't have to deal with Complex Decoding of x86 this saves tons of time.

The x86 decoding penalty is minimized with the clustered decode, their real problem is lack of proper leadership resulting in poor execution.

It was thought by some "impossible" for x86 to go OoOE, then Intel managed to get the P6 out not only with OoOE but they released the 0.35 micron process version along with the expected 0.5 micron process dashing hopes of RISC vendors of expanding their market. Back then they were firing on all cylinders.

Even in early 2000's, they were the first to adopt ALL memory and IO standards. They lost all of that, and it's been almost ten years ago where they started losing even to AMD!

The fact that in the modern age where Moore's Law gains are really slowing down they got 20% gains with Sunny and Golden Cove cores, while in the Sandy Bridge to Skylake era they barely eeked out 10% gains shows that they intentionally sabotaged themselves in the name of more profits and appeasing shareholders.

 

[Hulk]

The x86 decoding penalty is minimized with the clustered decode, their real problem is lack of proper leadership resulting in poor execution.

It was thought by some "impossible" for x86 to go OoOE, then Intel managed to get the P6 out not only with OoOE but they released the 0.35 micron process version along with the expected 0.5 micron process dashing hopes of RISC vendors of expanding their market. Back then they were firing on all cylinders.

Even in early 2000's, they were the first to adopt ALL memory and IO standards. They lost all of that, and it's been almost ten years ago where they started losing even to AMD!

The fact that in the modern age where Moore's Law gains are really slowing down they got 20% gains with Sunny and Golden Cove cores, while in the Sandy Bridge to Skylake era they barely eeked out 10% gains shows that they intentionally sabotaged themselves in the name of more profits and appeasing shareholders.

The old Intel was determined to maintain a technological lead.

The new Intel is determined to create the impression of a lead.

 

[lightisgood]

Intel Showcases Panther Lake SoCs For The First Time To The Public, Team Blue Looks Determined For A Successful Release

Intel's Panther Lake SoCs have finally made an appearance in public, as Team Blue displays the CPU tile at Embedded World 2025

wccftech.com

This is beautiful tile design (c.f. MTL)...
Maybe Foveros is shrunk to 25um bump-pitch from 36um.

 

[511]

The x86 decoding penalty is minimized with the clustered decode, their real problem is lack of proper leadership resulting in poor execution.

It was thought by some "impossible" for x86 to go OoOE, then Intel managed to get the P6 out not only with OoOE but they released the 0.35 micron process version along with the expected 0.5 micron process dashing hopes of RISC vendors of expanding their market. Back then they were firing on all cylinders.

Even in early 2000's, they were the first to adopt ALL memory and IO standards. They lost all of that, and it's been almost ten years ago where they started losing even to AMD!

The fact that in the modern age where Moore's Law gains are really slowing down they got 20% gains with Sunny and Golden Cove cores, while in the Sandy Bridge to Skylake era they barely eeked out 10% gains shows that they intentionally sabotaged themselves in the name of more profits and appeasing shareholders.

I am not saying about penalty but the time and resources it take to maintain it here is the comment from one of Intel employees who worked on it.

https://twitter.com/x/status/1851419593702871094

 

[Hulk]

Intel Showcases Panther Lake SoCs For The First Time To The Public, Team Blue Looks Determined For A Successful Release

Intel's Panther Lake SoCs have finally made an appearance in public, as Team Blue displays the CPU tile at Embedded World 2025

wccftech.com

This is beautiful tile design (c.f. MTL)...
Maybe Foveros is shrunk to 25um bump-pitch from 36um.

I don't understand how it "launches" H2 2025 and "gets into the hands of consumers" in 2026?

I guess we have a new definition for the meaning of the word launch.

What is beautiful about it? We know nothing about the architecture. I guess it looks like a nice rectangle and they might have gotten rid of the filler tile so that means it's beautiful? Beautiful to me would be amazingly elegant and efficient architecture. Core2Duo was beautiful because it pushed the technology of the day to a new level of both performance and efficiency.

Okay. Now I believe Intel has pulled out of it's death spiral.

Not.

 

[Nothingness]

What is beautiful about it? We know nothing about the architecture.

We know the architecture, but not the micro-architecture

https://cdrdv2.intel.com/v1/dl/getContent/671368

- RDMSRLIST/WRMSRLIST/WRMSRNS
- Virtualization of guest accesses to IA32_SPEC_CTRL
- Flexible Return and Event Delivery (FRED) and the LKGS instruction
- NMI-Source Reporting
- Architectural PEBS

Sexy, heh?

 

[511]

I don't understand how it "launches" H2 2025 and "gets into the hands of consumers" in 2026?

One answer it launches Like Lunar Lake or EEP (Early Enables Program) basically few laptops

I guess we have a new definition for the meaning of the word launch.

What is beautiful about it? We know nothing about the architecture. I guess it looks like a nice rectangle and they might have gotten rid of the filler tile so that means it's beautiful? Beautiful to me would be amazingly elegant and efficient architecture. Core2Duo was beautiful because it pushed the technology of the day to a new level of both performance and efficiency.

Okay. Now I believe Intel has pulled out of it's death spiral.

Not.

I can't stop laughing reading this 🤣

 

[adroc_thurston]

I don't understand how it "launches" H2 2025 and "gets into the hands of consumers" in 2026?

3 designs in H2'25, everything else CES'26 onwards.

 

[511]

3 designs in H2'25, everything else CES'26 onwards.

It's not AMD we can expect the HP/ACER/DELL/Lenovo/MSI/Asus every Major Intel OEM they will ship roughly 2-3 Million Panther Lake in Q4 25 Like they did with Lunar Lake.

 

[adroc_thurston]

It's not AMD we can expect the HP/ACER/DELL/Lenovo/MSI/Asus every Major Intel OEM they will ship roughly 2-3 Million Panther Lake in Q4 25 Like they did with Lunar Lake.

2-3m is like 1% of the PC TAM.
Op success?

 

[poke01]

That 12Xe GPU SKU better not be for Ultra 9. If it is then it’s only for show. Those laptops will be expensive.

 

[MoistOintment]

2-3m is like 1% of the PC TAM.
Op success?

2m-3m per quarter is 4% of the TAM. 2M - 3M isn't unreasonable for Q1 26 as most models will likely launch in late January - February.

I think 20M PTL sales is easily achievable in the first 12 months, considering MTL launched in December 2023 and hit the 15 million mark by August of 2024.

 

[Hulk]

We know the architecture, but not the micro-architecture

https://cdrdv2.intel.com/v1/dl/getContent/671368

- RDMSRLIST/WRMSRLIST/WRMSRNS
- Virtualization of guest accesses to IA32_SPEC_CTRL
- Flexible Return and Event Delivery (FRED) and the LKGS instruction
- NMI-Source Reporting
- Architectural PEBS

Sexy, heh?

I'm in love.

 

[igor_kavinski]

I can't stop laughing reading this 🤣

I'm betting Hulk's weekly Youtube podcast would be a roaring success

 

[511]

2-3m is like 1% of the PC TAM.
Op success?

Yeah kind of but 2-3 millions are lots of Chips someone can't go around and say they barely shipped Panther Lake