Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[Kepler_L2]

Cypress Cove: 18%
Willow Cove: 0%
Golden Cove: 19%
Redwood Cove: 0%(arguably minus)
Lion Cove: ~10%

Based on this trajectory Cougar Cove is the 0% shrink and Panther Cove is maybe 10%.

Do you know Exist is saying that 20A was so bad that it would have resulted in a worse Arrowlake?

AFAIK 20A ARL-S samples had an FMax of 5.0 GHz.

 

[gaav87]

How so? I'm losing money on my INTC investments but I knew it was a risk. And I don't see ARL-S having much impact on their stock value. It's more the laptop parts that will matter.

Should have bought for 19.6 like me xD

 

[511]

Should have bought for 19.6 like me xD

The only cope is 18A

 

[Philste]

Gelsinger started his return to Intel beginning of February 2021. That is 3.5 years before arrow lake launch.
Might still be too late to radically change arrow lake, but certainly enough time to influence it.

Don't forget how crappy Intels execution was/is. MTL and ARL are both a year late. MTL Tape in was in 1H 21 (official Twitter Post by Intel) and tape out around Alder Lake Launch in September 2021. ARL is MTL with new Core Archs on the Compute Tile. So yeah, Pat didn't have much influence on that one.

 

[511]

Don't forget how crappy Intels execution was/is. MTL and ARL are both a year late. MTL Tape in was in 1H 21 (official Twitter Post by Intel) and tape out around Alder Lake Launch in September 2021. ARL is MTL with new Core Archs on the Compute Tile. So yeah, Pat didn't have much influence on that one.

Its become better not that good vs AMD/Nvidia though PTL/Clearwater seems healthy but we will see how it turns out 12Xe3 should be good and Darkmont without ARL Issue

It's surprising how uncore is messing the Cores along with slow L3

 

[Henry swagger]

Golden eagle will finish off the p core team.. lion cove is an embarrassment.. apple is giving cpu design lessons to intel 🙄

 

[Ranulf]

"$404 value cannot be found."

Hah, they actually priced it at $404 on NE. Crazy.

 

[gaav87]

Its become better not that good vs AMD/Nvidia though PTL/Clearwater seems healthy but we will see how it turns out 12Xe3 should be good and Darkmont without ARL Issue

It's surprising how uncore is messing the Cores along with slow L3

Idk from the kernel driver access i have xe3_lpg has same MOCS table's as xe2_lpg. So same cache and memory guess no gddr7 for celestial. My guess they just increased core count per slice vs xe2.

 

[Kepler_L2]

Idk from the kernel driver access i have xe3_lpg has same MOCS table's as xe2_lpg. So same cache and memory guess no gddr7 for celestial. My guess they just increased core count per slice vs xe2.

Celestial dGPU would be Xe3_HPG. But rumor is that it's cancelled anyway.

 

[lightmanek]

Your honesty is refreshing.

GN has their 265K review up. TLDW = "$404 value cannot be found."

I cracked hard at "Error Lake" pun at the start of the video 😅

 

[gaav87]

Celestial dGPU would be Xe3_HPG. But rumor is that it's cancelled anyway.

I was talking about xe3_lpg for ptl-uh. There is zero info on xe3_hpg in drivers.
PS.
bmg is on B0 since 2 weeks ago at LAST.

 

[DrMrLordX]

AFAIK 20A ARL-S samples had an FMax of 5.0 GHz.

Any word on if power would have been better?

 

[igor_kavinski]

DC variant of LNC at Al will still feature SMT.

So they dropped HT in consumer Arrow Lake to dial back power consumption?

 

[Tigerick]

Above picture said a thousand words:- 20A version of Arrow Lake is on track for H2'24.... Pat either don't know what the true progress of 20A is or simply promised something he knew won't be coming. I let you guys be a judge

 

[Kepler_L2]

Any word on if power would have been better?

No clue.

 

[511]

View attachment 110391

Above picture said a thousand words:- 20A version of Arrow Lake is on track for H2'24.... Pat either don't know what the true progress of 20A is or simply promised something he knew won't be coming. I let you guys be a judge

Wait Arrow lake Intel 3 seems fishy Looks like i3 are Intel 3

 

[cebri1]

Wait Arrow lake Intel 3 seems fishy Looks like i3 are Intel 3

MTL refresh “Arrow Lake” is on Intel 3. Laptop only.

 

[511]

MTL refresh “Arrow Lake” is on Intel 3. Laptop only.

Ahh right ARL-U

 

[cannedlake240]

View attachment 110391

Above picture said a thousand words:- 20A version of Arrow Lake is on track for H2'24.... Pat either don't know what the true progress of 20A is or simply promised something he knew won't be coming. I let you guys be a judge

They know cancelling nodes absolutely won't help improve their fabs reputation. So it was more of a financial decision. Even if the yields weren't up to hvm standards they'd still do a paper launch as a tiny portion of the whole ARL supply.

 

[Meteor Late]

Diamond uses Panther cove which is an update over Cougar Cove which itself is update over Lion Cove

TSMC Nodes aren't easy to work with at High voltage
View attachment 110382

This is the first iteration of TSMC 3nm, N3B, the worst performing version of their 3nm. Please tell me what was the performance of Intel's first iteration of 14nm, 10nm, Intel 4?
I mean, it sounds great seeing how high Intel chips can get to clock, until you realize how many refinements their node needs to do so.

 

[lopri]

https://twitter.com/x/status/1849852583608975695

I am now interested in which of the P/E cores were cut on 245K. (and 265K to a lesser extent)

 

[Hulk]

View attachment 110391

Above picture said a thousand words:- 20A version of Arrow Lake is on track for H2'24.... Pat either don't know what the true progress of 20A is or simply promised something he knew won't be coming. I let you guys be a judge

Read my lips.
"5 nodes in 4 years."

 

[IEC]

Roman heats up some Arrow Lake chips above 160C to melt some indium solder and delid chips:

Delidding tools seem to cost $arm and $leg due to 90 Euro cost of just the heating/temp sensor element alone so probably not worth it especially given the cooling doesn't seem to significantly limit OC potential.

Doing the old mechanical fatigue method apparently leads to dead chips. Thus the need to melt the indium solder to minimize the mechanical stress.

 

[cebri1]

Roman heats up some Arrow Lake chips above 160C to melt some indium solder and delid chips:

Delidding tools seem to cost $arm and $leg due to 90 Euro cost of just the heating/temp sensor element alone so probably not worth it especially given the cooling doesn't seem to significantly limit OC potential.

Doing the old mechanical fatigue method apparently leads to dead chips. Thus the need to melt the indium solder to minimize the mechanical stress.

Deliding reduces temps by 20C :O

Edit: WTF

 

[The Hardcard]

View attachment 110391

Above picture said a thousand words:- 20A version of Arrow Lake is on track for H2'24.... Pat either don't know what the true progress of 20A is or simply promised something he knew won't be coming. I let you guys be a judge

Or maybe he got confronted with more stark financial realities after that presentation.