Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.





Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[dullard]

Still the delusion regarding 20A. Why would such an AWESOMESAUCE node only be in 6+8 and only in desktop? Because it's not that good.

And there, @Wolverine2349, you now have your conspiracy answer that was predicted.

Conspiracy answer: they are using TSMC, therefore Intel's 20A yield is too low to make any big chips. Of course, there is zero evidence for it, but you'll see that thought a lot.

 

[SiliconFly]

You cannot have a F1 car with a 600 hp V16 alone. You need the chassis to be aerodynamic, the wheels to be large and smooth, the vehicle be very light, etc, etc.

Intel was the leader in the last four decades. It's not like they're not aware of how foundries work! And looking at their current execution frenzy, I think they may do well in the future.

They have refined and optimised 10nm so much, it's as if blood has been squeezes out of a stone.

So true!

They are fast iterating to catch up and exceed competitors. That's the sole purpose of Intel 4 and 20A.

That part I might have to agree.

 

[dullard]

Lunar Lake
8 core Xe2 GPU
8 MB GPU L2 cache
8 MB SLC
LPDDR5X-8533 + 128 bit = 136 GB/s

Panther Lake
12 core Xe3 GPU

Panther Lake has a significantly beefed up GPU. How are they going to feed it?

Supposedly it's going to stick to LPDDR5X, and not upgrade to LPDDR6.

Assuming you are correct that they stick with LPDDR5X, LPDDR5X-9600 is already available from Micron and SK hynix. That would give 12.5% more throughput. That isn't a lot more given the increased memory demands, but it would help.

Micron and SK hynix Ship LPDDR5-9600 Memory for Next-Gen Smartphones

www.anandtech.com

Samsung is sampling LPDDR5X-9600 too: https://semiconductor.samsung.com/dram/lpddr/lpddr5x/k3kl5l50em-bgcv/ and they have announced LPDDR5X-10700 (25% more frequency than 8533 memory): https://www.anandtech.com/show/21354/samsung-unveils-world-s-fastest-lpddr5x-memory-10-7-gt-s

 

[Magio]

LNL supply would be very limited until next year:

https://twitter.com/x/status/1808386960471498945

EEP might means 'exclusive' or 'preemptive', only few top vendors have privilege and get on LNL supply earlier.

Considering LNL will be a premium product that targets a single segment, it probably makes sense to focus initial supply on a few halo products from top OEMs (Dell, Lenovo, HP and Asus for sure, plus the LNL Claw from MSI, ...), but hopefully those are widely available by early Q4 and not paper launches.

 

[Hulk]

If the Lunar Lake die is larger than the ARL compute die then yields (and timing) could be reasons for LNL being on a TMSC node while ARL, at least some tiles, might be Intel.

 

[LightningZ71]

There is the possibility that Panther Lake will have a different memory configuration than Lunar Lake. If the iGPU portion is going to have 50% more Xe cores, and they will have more transistors in each one, and if the CPU portion is also expanded, it stands to reason that the package will grow. A larger processor package will give space for an additional memory chip, meaning that there is a possibility of having a 192 bit bus (3 x 64, 6 X 32 etc). That would better match the bandwidth needs of the expanded GPU and faster CPU.

 

[TwistedAndy]

There is the possibility that Panther Lake will have a different memory configuration than Lunar Lake. If the iGPU portion is going to have 50% more Xe cores, and they will have more transistors in each one, and if the CPU portion is also expanded, it stands to reason that the package will grow. A larger processor package will give space for an additional memory chip, meaning that there is a possibility of having a 192 bit bus (3 x 64, 6 X 32 etc). That would better match the bandwidth needs of the expanded GPU and faster CPU.

Panther Lake will use the 192-bit LPDDR6 CAMM2 memory (8x24 bit).

There's no option to use the old 128-bit interface (8x16-bit) because LPDDR6 has 24-bit channels:

 

[DavidC1]

If the Lunar Lake die is larger than the ARL compute die then yields (and timing) could be reasons for LNL being on a TMSC node while ARL, at least some tiles, might be Intel.

Let's see.

If I was Gelsinger, I would have made the same decision if I wanted to get to 18A quickly. Why would I care if it doesn't meet performance goals nor yield?

Normally you'd go through all the steps for yield and performance of the part, but they don't need to in this case. As soon as they work, then the work can start on the real ones, that is, Intel 3 and 18A.

How do you think they are reiterating so quickly otherwise?

Also Lunarlake can only use Intel 3 or 18A, because the compute tile has more library requirements than 4 or 20A. Intel 3 is clearly much less dense than N3B for example. 18A might close the gap, but that's not ready in 2024.

I don't get why people don't get that refinements are needed to get it to a fully functional product. Meteorlake to this day doesn't seem fully refined does it? The refinements and polish for a process may be the difference between being leadership or being Cannonlake 10nm all over again. But it doesn't matter in the long run if 20A = CNL 10nm, because 18A will come anyway.

The reason Cannonlake came out in a limited format is for yield learning so they can get stop the bleed and get the real one out. Would not be surprised if that's why only 6+8 -S is 20A. Cannonlake Part Deux. None of the high level advancements on CNL 10nm mattered. None of it.

Also it seems many people here haven't learned from the Zen 5 hype(and to a lesser extent, Lion Cove). To be at 20%, Arrowlake's LNC needs to be a full 5% faster per clock than in Lunarlake, when it has tile deficiency to make up for. Ah you know what they say! Most people are stubborn and never learn!

Ok how about this? LNL's LNC = 14% faster over Redwood Cove in MTL and ARL's LNC = 20% faster than RWC in MTL, meaning Arrowlake's LNC is 17% faster than Golden Cove.

 

[FlameTail]

Panther Lake will use the 192-bit LPDDR6 CAMM2 memory (8x24 bit).

There's no option to use the old 128-bit interface (8x16-bit) because LPDDR6 has 24-bit channels:

View attachment 102339

Panther Lake will not use LPDDR6, I hear.

 

[Doug S]

The reason Cannonlake came out in a limited format is for yield learning so they can get stop the bleed and get the real one out.

No it was because they'd promised Wall Street they'd FINALLY deliver 10nm chips in H1 2018, and after several broken promises they knew it would impact the stock price (i.e. their bonuses) if they blew past yet another deadline with nothing to show.

So they released a single SKU in a low volume non performance sensitive embedded market just so they could claim "we're shipping", even though they knew 10nm was nowhere near ready. There was no "learning" involved in this, it was simply a scam launch. That is made evident by the fact that Cannon Lake was just this single SKU and the next 10nm part didn't arrive until sixteen months had passed!

 

[Kepler_L2]

Panther Lake will use the 192-bit LPDDR6 CAMM2 memory (8x24 bit).

There's no option to use the old 128-bit interface (8x16-bit) because LPDDR6 has 24-bit channels:

View attachment 102339

PTL is too early for LPDDR6.

 

[Bouowmx]

Panther Lake will use the 192-bit LPDDR6 CAMM2 memory (8x24 bit).

There's no option to use the old 128-bit interface (8x16-bit) because LPDDR6 has 24-bit channels:

I did not realize this change for LPDDR6. Desktops with 3-DIMM memory kits in future?

 

[FlameTail]

I did not realize this change for LPDDR6. Desktops with 3-DIMM memory kits in future?

LPDDR doesn't come in DIMMs

 

[FlameTail]

According to this video:

Intel has supposedly started to seed Lunar Lake dev kits to developers. Does this mean that if someone is able to get their hands on one of those dev kits, they could run some early tests to ascertain how good Lunar Lake is?

 

[jpiniero]

No it was because they'd promised Wall Street they'd FINALLY deliver 10nm chips in H1 2018, and after several broken promises they knew it would impact the stock price (i.e. their bonuses) if they blew past yet another deadline with nothing to show.

More like CYA so "Investors" couldn't sue when they boasted about being able to ship 10 nm that year.

So they released a single SKU in a low volume non performance sensitive embedded market just so they could claim "we're shipping", even though they knew 10nm was nowhere near ready. There was no "learning" involved in this, it was simply a scam launch. That is made evident by the fact that Cannon Lake was just this single SKU and the next 10nm part didn't arrive until sixteen months had passed!

IIRC, Chinese (Education) market.

You know, it would have been interesting what they could have been able to do if they had something like Meteor Lake... where 80% of the chip is fabbed at TSMC.

 

[Bouowmx]

LPDDR doesn't come in DIMMs

yes, but whatever desktop parts repackaged from mobile will have 192-bit memory already present, to be filled with standard DDR

 

[TwistedAndy]

PTL is too early for LPDDR6.

Panther Lake is a 2026 product that is not Pin-to-Pin compatible with Arrow Lake, according to the recent Clevo's leak:



I don't see any good reason to change the pin layout for Panther Lake and then change it again for the LPDDR6 support in the next platform a year later.

Intel will probably switch to LPDDR6 with Panther Lake and use the next 2027 mobile platform as a drop-in replacement. Many OEMs are used to Intel's two-year cycles (new platform -> drop-in refresh -> new platform)

 

[Doug S]

yes, but whatever desktop parts repackaged from mobile will have 192-bit memory already present, to be filled with standard DDR

No they won't, because you can't use standard DDR in CPUs that have LPDDR controllers. If they make a version that takes standard DDR it'll require a different controller, and there's no reason they would stick with 192 bits wide in that case.

Of course that would only be valid for DDR6, because I would not assume that DDR6 DIMMs will be 64 bits wide. I think they will be 96 bits, with four 24 bit channels organized in the same way LPDDR6 is. I think DDR6 will be a server/high end workstation only part. Regular desktops and even high end gamer setups will use LPDDR6 not DDR6.

 

[FlameTail]

What is TWL-N?

 

[FlameTail]

Of course that would only be valid for DDR6, because I would not assume that DDR6 DIMMs will be 64 bits wide. I think they will be 96 bits, with four 24 bit channels organized in the same way LPDDR6 is. I think DDR6 will be a server/high end workstation only part. Regular desktops and even high end gamer setups will use LPDDR6 not DDR6

DDR6 will be 64 bits, IIRC.

 

[TESKATLIPOKA]

Official slide, yet they don't even bother to check If there is no mistake.

Supports type 3 or 4 MB

That should have been PCB, If I am not mistaken.

 

[coercitiv]

Panther Lake will use the 192-bit LPDDR6 CAMM2 memory (8x24 bit).

Intel will probably switch to LPDDR6 with Panther Lake

I've seen this pattern in some other posts of yours, please stop presenting speculation as facts. Even if some of us understand you're only voicing your own (well informed) opinion and making an educated guess, other people on this forum and especially infrequent visitors will eventually mistake these for facts/leaks.

If we lack credible leaks or announcements to support a claim, we can always use certain types of phrasing to let others know speculation is involved. This is not a sign of weakness or uncertainty, it's a sign of respect for the rest of the community, and will probably avoid unnecessary additional discussions when folks dispute a claim.

For what it's worth, I really like your posts and appreciate the details you go in when explaining your PoV.

 

[Gideon]

yes, but whatever desktop parts repackaged from mobile will have 192-bit memory already present, to be filled with standard DDR

Hopefully, but they might just as well just keep using dual channel with DDR5 or DDR5 CAMM 2:

https://www.pcgamer.com/hardware/memory/kingston-gave-me-my-first-glimpse-of-camm2-ddr5-ram-at-computex-2024-along-with-some-ai-gen-race-drivers-and-a-very-heavy-f1-theme/

I personally wouldn't mind 3-channel (DDR5) memory support for high-end chips at all. High-end iGPUs would massively benefit from this, as woud the highest end multicore CPUs. I'm just not sure Intel or AMD will go that route.

 

[Ghostsonplanets]

What is TWL-N?

ADL-N refresh

WDL is the successor using Darkmont cores.

 

[TwistedAndy]

If we lack credible leaks or announcements to support a claim, we can always use certain types of phrasing to let others know speculation is involved. This is not a sign of weakness or uncertainty, it's a sign of respect for the rest of the community, and will probably avoid unnecessary additional discussions when folks dispute a claim.

I added a credible leak to support my claim

Let's analyze that chart closely. Intel is going to update the pinout for PTL-U and PTL-H. This platform will be released in 2026 and actual devices will appear in Q1 or Q2 2026. The following platform released in 2027 will use the same pinout as Panther Lake.

Intel did that with CFL/TGL, ADL/RPL, MTL/ARL, and will continue with PTL and the next platform. It's too expensive for OEMs to redesign a platform every year.

DDR5/LPDDR5 is currently 4-5 years old and slowly reaching its limits. In 2026 and 2027, it will be completely obsolete, especially considering the AI hype. Those "++TOPS" we see on the chart require more memory bandwidth, so LNL is using one of the fastest LPDDR5 memory.

LPDDR6 is expected to be introduced this year. Rumors suggest that Snapdragon 4 Gen 4 and Apple A18 will use LPDDR6. I do not see any reason why it will not be available in 2026.

If we consider other aspects, the leaked chart tells us more information:
1. ARL can use the same SoC tile as Meteor Lake with DDR5/LPDDR5 memory. That's why there is no "++TOPS" label.
2. ARL Refresh will be more than a clock bump. Intel plans to redesign at least the SoC tile, add a more powerful NPU, and introduce the LPDDR6 support. That's why there's a note "Not Pin to Pin"
3. ARL-HX is the most confusing part here. For some reason, RPL-HX is not pin-to-pin compatible with ARL-HX. So, we will have a situation when the design should be updated for ARL-HX and once again for ARL-HX Refresh for the LPDDR6 CAMM2 support. It's not a big issue because the HX laptops are usually more expensive.
4. LNL will not have a direct successor. It will probably be replaced with the refreshed version of PTL-U, which has a new SoC tile and a larger NPU.
5. My biggest concern here is the ARL-H refresh. I'm not sure how Intel will manage this transition. Probably, the initial version of ARL-H will be offered as a drop-in replacement for the current MTL-H platforms (with the same NPU), but the vendors will be able to release refreshed ARL-H platforms a bit later. It still looks weird to me.
6. Technically, ARL refresh and Panther Lake can support both LPDDR5/LPDDR5X and LPDDR6, but I'm not entirely sure here.