Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

[Tigerick]

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	12 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop & Mobile H&HX	Mobile U Only	Mobile H
Process Node	Intel 4	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	8P + 16E	4P + 4E	4P + 8E
LLC	24 MB	36 MB ?	12 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

[trivik12]

Cryptic comment from Raichu.

https://twitter.com/x/status/1767987028040495397

 

[Hitman928]

Cryptic comment from Raichu.

https://twitter.com/x/status/1767987028040495397

Tweet is unavailable for me.

 

[SiliconFly]

Regarding that, here's a theory.

LNL has LP E-cores, not normal E-cores which means they will likely not participate in heavy MT tasks, just like the two LP E-cores in MTL are programmed to take a backseat in everything except watching videos or browsing.

So if the LNL LP E-cores are programmed identically, we come to a startling realization. That 1.5X MT perf increase over MTL-U is ALL LNC P-cores!!!!

I think that might be why adroc considers LNL not terribad.

Oh wow! That sounds awesome. I wondered abt it at first, then dismissed it assuming those E cores are just regular Skymont cores (not LPE cores).

If true, LNC sounds extremely promising. No wonder Intel has put LNC in LNL, ARL, PNL, NVL, DNR, etc. It shows their confidence level in the new arch as they're clearly betting everything on LNC. Looks like LNC is gonna be a killer core architecture!

But there's still one concern. LNL has 4P cores, whereas, MTL-U has only 2P cores. Is this why there's a 1.5X MT performance bump? Or am I missing something? Can someone please extrapolate the performance of LNC based on how LNL 4P+4LPE is 1.5X faster that a 15W 2P+8E MTL-U 155U or 135U?

 

[Abwx]

I knew that Gracemont was area efficient but I did not know that below about 3.2GHz it is more power efficient than Golden Cove.

Is it if we compare at same throughput, because comparing at a same frequency without specifying the throughput is irrelevant.

If a core A has 25% higher throughput than core B at same frequency then you can downclock the former by 20% wich will reduce its power by about 35-40% while still matching core B s throughput.

 

[dullard]

As for the E core frequency, you can clock them where ever you want with a K chip, right?

I think you can, but maybe someone else can chime in (I don't have any K chips as I don't overclock). But, even if you can you are already in a losing position. Power is roughly proportional to V^2 * f. Even if you can adjust the frequency, f, having the voltage being squared has a much more important role than just frequency (assuming voltage is fixed to make the P-cores perform well).

 

[igor_kavinski]

Can someone please extrapolate the performance of LNC based on how LNL 4P+4LPE is 1.5X faster that a 15W 2P+8E MTL-U 155U or 135U?

Keeping things simple and assuming that LNL was compared to 125U and power never exceeded 15W, this means MTL P-cores were stuck at 1.3 GHz and E-cores at 0.8 GHz. Eight E-cores perform about as much as 4 P-cores max so 4 LNL P-cores are competing against 6 effective RWC P-cores. LNC is so performant that it not only overcomes the deficit of two P-cores but goes above and beyond and posts 1.5X higher MT score at 15W.

DISCLAIMER: All speculation based on the assumption that the LNL LPE cores are not participating at all.

 

[SpudLobby]

On LNL: what is the actual power figure where it attains + 50%? Is it actually 15-17W ish? In theory the performance improvement iso-power should be roughly similar (reasonable range) throughout the power ranges but it just depends, it’s an arch change and core config change, different node.

But much more interestingly; what does MTL-U 125U score at
15W, 25W, 35W?
In GB5 MT?

Do we even have any leaks?

 

[Philste]

Cryptic comment from Raichu.

Also this one:

Pretty sure it's about Sierra Forest. He leaked Sierra Forest AP last summer in a cryptic Tweet about giant, nearly 300 feet tall trees. Nearly 300 feet meant nearly 300 Cores. The first part of this one from today is obvious, so we should expect SRF Launch in April (I think Intel Vision is in April). But what could the 3 meters mean?

 

[H433x0n]

Also this one:View attachment 95332

Pretty sure it's about Sierra Forest. He leaked Sierra Forest AP last summer in a cryptic Tweet about giant, nearly 300 feet tall trees. Nearly 300 feet meant nearly 300 Cores. The first part of this one from today is obvious, so we should expect SRF Launch in April (I think Intel Vision is in April). But what could the 3 meters mean?

Whoosh

That went right over my head. I didn’t even think about it in the terms of a leak.

 

[gdansk]

What if he simply likes trees?
I don't follow him but it's best to more clear than talking about blooming flowers if you know something.

 

[ashFTW]

But what could the 3 meters mean?

3 GHz?

 

[Markfw]

I am really curious to know how 288 e-cores is going to do vs 128 Zen4c cores. and avx-512 as well.

 

[Hulk]

Is it if we compare at same throughput, because comparing at a same frequency without specifying the throughput is irrelevant.

If a core A has 25% higher throughput than core B at same frequency then you can downclock the former by 20% wich will reduce its power by about 35-40% while still matching core B s throughput.

Did you look at the graph to which I was referring? It showed work (Joules), not rate of work.

 

[Glo.]

Also this one:View attachment 95332

But what could the 3 meters mean?

Isn't it obvious what you need to have in order to obtain it?

 

[Hulk]

Who is Raichu? Where is he located and does he actually have these parts or inside information? Why all of the teasing? It's weird.

 

[mikk]

View attachment 95263
Regarding that, here's a theory.

LNL has LP E-cores, not normal E-cores which means they will likely not participate in heavy MT tasks, just like the two LP E-cores in MTL are programmed to take a backseat in everything except watching videos or browsing.

View attachment 95264

So if the LNL LP E-cores are programmed identically, we come to a startling realization. That 1.5X MT perf increase over MTL-U is ALL LNC P-cores!!!!

I think that might be why adroc considers LNL not terribad.

Is there a rule that says LP E cores are not allowed to be used in heavy MT tasks? It didn't make sense on MTL for various reasons. Since Skymont moved into the compute tile on Lunar Lake you can be sure it will participate in heavy MT tasks. They won't waste 4 cores for nothing and certainly not on a chip with only 4 P cores.

 

[Abwx]

Did you look at the graph to which I was referring? It showed work (Joules), not rate of work.

This is not the work, look better, it s the energy in joules consumed at a given frequency, to have the real picture you should do a ponderation with the throughput in function of the frequency, wich is not done in this graph.

Edit : If it were energy efficency/task then 4 P cores at 2.5GHz would require as much energy than 4 e cores at 3Ghz to do the task, that s about impossible.

At same frequency a P core has 80% more throughput than a e core thanks to SMT, so you can downclock the P core down to 1.67Ghz to have the same throughput as one e core at 3Ghz, it s impossible that a e core can be even remotely as efficient as a P core since at 1.67Ghz a P core will use way lower power than a e core at 3GHz.

 

[Hulk]

This is not the work, look better, it s the energy in joules consumed at a given frequency, to have the real picture you should do a ponderation with the throughput in function of the frequency, wich is not done in this graph.

Edit : If it were energy efficency/task then 4 P cores at 2.5GHz would require as much energy than 4 e cores at 3Ghz to do the task, that s about impossible.

At same frequency a P core has 80% more throughput than a e core thanks to SMT, so you can downclock the P core down to 1.67Ghz to have the same throughput as one e core at 3Ghz, it s impossible that a e core can be even remotely as efficient as a P core since at 1.67Ghz a P core will use way lower power than a e core at 3GHz.

I don't think you understand the difference between work/energy and power/rate of energy based on your post.

The y-axis clearly states "joules," which is the amount of energy to compete the workload. Power is a rate of work, generally expressed as J/sec or Watts.

I can't speak to the veracity of the data but I do know that the graphs indicates work, not power. Keep in mind that the "throughput" of E vs P cores varies by application and is not constant.

 

[Henry swagger]

Who is Raichu? Where is he located and does he actually have these parts or inside information? Why all of the teasing? It's weird.

He has good intel sources.. and has a 85% hit rate with leaks

 

[Philste]

What if he simply likes trees?
I don't follow him but it's best to more clear than talking about blooming flowers if you know something.

This was his Leak for SRF-AP at the beginning of June 2023, more than 3 months before Pat showed it publicly:
I think @ashFTW is right, it might be 3GHz+. The Trees in the new pic from yesterday are nowhere near 3m, they are way higher.

 

[DavidC1]

Pretty sure it's about Sierra Forest. He leaked Sierra Forest AP last summer in a cryptic Tweet about giant, nearly 300 feet tall trees. Nearly 300 feet meant nearly 300 Cores. The first part of this one from today is obvious, so we should expect SRF Launch in April (I think Intel Vision is in April). But what could the 3 meters mean?

If your post is about Sierra Forest, then it's logical to conclude that "arrow coming earlier than previous work by about a month" would indicate that Arrowlake comes about a month earlier than Raptorlake did.

If that's RPL-R then that's in October. If it's RPL it's in September. If it's Meteorlake then it's November.

3 GHz?

This seems like a very good speculation as well.

"Easy" to get 3 and launching in April rather than the commonly expected June for H1 would indicate a product that would turn out better than expected(especially those that think E cores are literally mere step above trash).

With Zen 4's Integer lead being 20% over Gracemont, SRF with 10% more cores and 10% higher clocks would make it very competitive, especially in Cloud.

Geekbench's results are even closer

N100 3.4GHz Integer: 1019
Epyc 9754 Integer: 1060

Default string Default string - Geekbench

Benchmark results for a Default string Default string with an Intel N100 processor.

browser.geekbench.com

ASUSTeK COMPUTER INC. RS500A-E12-RS12U - Geekbench

Benchmark results for an ASUSTeK COMPUTER INC. RS500A-E12-RS12U with an AMD EPYC 9754 processor.

browser.geekbench.com

Intel Vision is April 8 to 9th.

 

[DavidC1]

The lesser known impact of Sierra Forest is that it comes merely 1H after they say Intel 3 is in production, when for Intel 4 it took a year.

I think there's also a significance in saying 18A is 1H ahead of 20A. 20A product comes in H2 2024 with Arrowlake. Logically, 18A product is Clearwater Forest in H1 2025. Cutting the gap alludes to improved design execution.

288 cores of Skymont that's on par with Golden Cove in average(Int and FP), on 18A in 2025 will truly mark "undisputed leadership").

 

[reggie_fils_aime]

If it is so horrible, why did you buy it??

Where did I say it was horrible? I bought ADL the year it came out, loved it, and probably would've stuck on it until next year before the warping took out my CPU PCIe lanes. My issue with E cores is that they're a bad solution to a problem that intel has been papering over for more than a decade, i.e they can't innovate on smaller nodes and are left with the brute force option to make up performance. I would've probably upgraded to 14th gen if they released a 12P+4-8E core SKU, but I don't have much interest in an 8-core processor taped to the silicon equivalent of a 7 year old Xeon E5.

Intel, and their many misadventures in packaging, has lead to a giant mess in terms of the composition of their desktop chips. This is vs. AMD who has, somehow, managed to put 16 whole big cores on a consumer grade platform without burning down our houses. Right now, it feels like we're on the precipice of another point of inflection in the market, similar to when Motorola started to really lose touch in the early-mid 90s, or IBM at the tail end of the PowerPC era. Intel needs to execute on more than one product launch every 5 years if they want to survive.

 

[dullard]

3 GHz?

I think Intel 3 seems to be what was intended. Because, well, Sierra Forest is on Intel 3.

 

[dullard]

The lesser known impact of Sierra Forest is that it comes merely 1H after they say Intel 3 is in production, when for Intel 4 it took a year....Cutting the gap alludes to improved design execution.

You might be reading too much into the exact timings for released chips. Intel had too little fab capability. For quite a while Intel did not have enough lithography equipment for large scale production on Intel 4 and Fab 9 for its Foveros packaging just came on line. https://www.anandtech.com/show/21246/intels-foveros-advanced-packaging-fab-9-starts-operations Both meant that Intel could only build small amounts of Meteor Lake chips.

Basically Intel had Intel 4 ready a long time before it was released, but not enough capacity to actually build it in volume. Simply improving fab capacity is a long ways away from proving that there is "improved design execution".