Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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PantherLake.png

LNL.png

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E2CPU + IOD + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Clockspeed.png
 
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SiliconFly

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Now that Intel has made Panther Lake official, can the mods pls add Panther Lake to the title of this thread?

You can name it "Intel Meteor Lake, Arrow Lake, Lunar Lake & Panther Lake Discussion Threads"

Or make it short & crisp like:

"Intel Meteor, Arrow, Lunar & Panther Lake Discussion Threads"
 
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SiliconFly

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Yes, there are multiple ways of producing a chiplet solution through various packaging technologies. They all have things in common though that the original C2Q didn't. I would also argue that Kaby Lake -G really wasn't a chiplet solution but Lakefield was.
Actually, Kaby Lake G is technically a chiplet package. But it lacks the bells & whistles of modern chiplet designs. But that doesn't mean it's not chiplets (by today's definition of chiplets).

When Kaby Lake G first came out, the term "chiplets" was neither widespread nor popular. Zen 2 was released later and made the term mainstream. But that doesn't mean Zen 2 is the first chiplet processor in the market.
 
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Hitman928

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Actually, Kaby Lake G is technically a chiplet package. But it lacks the bells & whistles of modern chiplet designs. But that doesn't mean it's not chiplets (by today's definition of chiplets).

KLK-G is kind of a half way point between traditional MCM and modern chiplets. The dies sit on the same substrate and do have inter-die communication links but they still act like completely separate solutions, just in close proximity versus placing them at the board level. Like I said, you could certainly argue that these are chiplets (and I think Intel calls them that now) and I wouldn't say it's wrong, but it's not quite the same thing as the modern chiplets we have from AMD/Intel/etc.
 
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SiliconFly

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KLK-G is kind of a half way point between traditional MCM and modern chiplets. The dies sit on the same substrate and do have inter-die communication links but they still act like completely separate solutions, just in close proximity versus placing them at the board level. Like I said, you could certainly argue that these are chiplets (and I think Intel calls them that now) and I wouldn't say it's wrong, but it's not quite the same thing as the modern chiplets we have from AMD/Intel/etc.
Kaby Lake G uses EMIB 1.0 which links both the CPU & GPU tile in the same package substrate. This is the definition of chiplets nowadays.

Sadly for Intel, the term "chiplets" came into widespread use only 1.5 years after the product was released. Thats the only issue.

(Source: anandtech, wikichip & link)
 

Tigerick

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Now that Intel has made Panther Lake official, can the mods pls add Panther Lake to the title of this thread?

You can name it "Intel Meteor Lake, Arrow Lake, Lunar Lake & Panther Lake Discussion Threads"

Or make it short & crisp like:

"Intel Meteor, Arrow, Lunar & Panther Lake Discussion Threads"
Done, hmm wonder what types of packaging Intel going to use on Panther Lake ??

Tiles based packaging is really not cost and power effective; and not really up to date. Like SoC tile in the MTL is still based on TSMC's N6 which is way too old in 2024, wonder how "powerful" can NPU be compared to the rest??? There are some tidbits about MTL issues which I hope would be address before shipping...

LNL packaging is way more simple and elegant...When Intel announced 5 nodes in 4 years, we know Intel is focused on CPU IP thus the rest of SoC is based on TSMC process. And all roads lead to 18A process, my question is does the 18A's PDK include GPU IP???
 
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Hitman928

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Kaby Lake G uses EMIB 1.0 which links both the CPU & GPU tile in the same package substrate. This is the definition of chiplets nowadays.

Sadly for Intel, the term "chiplets" came into widespread use only 1.5 years after the product was released. Thats the only issue.

(Source: anandtech, wikichip & link)

I already said that they were on the same substrate with inter-die connections, so not sure why your reply seems to restate what I just said, but the difference between it and more modern chiplets is that the GPU and CPU were designed, and Intel treated them, completely discretely and connected them with PCIe lanes on the substrate. Only the HBM and GPU were connected with EMIB but GPUs were being connected to HBM like this already (though EMIB was a better performing solution). The GPU had its own memory, IO, power delivery, etc. and communicated with the CPU exactly like it would have if it was on the motherboard instead.

More modern chiplets are designed with desegregation in mind, both in the chiplet and interconnect design. In the end, for the third time, I won't say it's wrong to call KBL-G a chiplet design, but it's not really the same thing that companies are doing with the solutions they actually started calling chiplets, which is why I called it kind of a halfway step.
 
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Geddagod

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Done, hmm wonder what types of packaging Intel going to use on Panther Lake ??

Tiles based packaging is really not cost and power effective; and not really up to date. Like SoC tile in the MTL is still based on TSMC's N6 which is way too old in 2024, wonder how "powerful" can NPU be compared to the rest??? There are some tidbits about MTL issues which I hope would be address before shipping...

LNL packaging is way more simple and elegant...When Intel announced 5 nodes in 4 years, we know Intel is focused on CPU IP thus the rest of SoC is based on TSMC process. And all roads lead to 18A process, my question is does the 18A's PDK include GPU IP???
Rumor is that PTL is going to combine the CPU and SOC tiles but leave the GPU tile separate.
 
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Hulk

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Tiles based packaging is really not cost and power effective; and not really up to date. Like SoC tile in the MTL is still based on TSMC's N6 which is way too old in 2024, wonder how "powerful" can NPU be compared to the rest??? There are some tidbits about MTL issues which I hope would be address before shipping...

As far as I understand the SoC is more or less what we used to call the motherboard chipset. Sure the NPU and Island LP E cores are added on but the Island E's are purely for power savings and I honestly don't think the NPU will be very powerful for Intel's first crack at this in the client space.

Are you implying the N6 node for the SoC will be holding that tile back in some meaningful way?
 

Mopetar

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That being said if "generational improvements" in IPC mean a few percent increase over Raptor Cove and Gracemont in the tiled configuration then that's pretty good for a first effort with so many "firsts" going on for Intel with this part.

The modular approach should make performance gains trivial in a sense, or rather just make if effectively free to have a higher performance tier than would be otherwise possible. If you have a monolithic chip with a lot of different parts you need all of those modules to be defect free and have top tier performance. Have a set of P-cores that can all run at 6 GHz, but a bunch of defective E-cores? Put it in a lesser bin because the top tier chip needs to have all of the E-cores working.

With the tile-based approach they can mix and match tiles based on their individual performance characteristics. It's far easier to assemble a top tier part from individual top tier pieces. Alternatively it also means you can make a better performing top tier. Trying to make a monolithic chip that had top 1% performance in all areas is next to impossible because so few chips will hit that criteria so instead you just go for a top 5% or 10% so you get enough chips that work for those targets. While tiles it's much easier to just pick the top 1% of all tiles and combine them.
 

SiliconFly

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Done, hmm wonder what types of packaging Intel going to use on Panther Lake ??

Tiles based packaging is really not cost and power effective; and not really up to date. Like SoC tile in the MTL is still based on TSMC's N6 which is way too old in 2024, wonder how "powerful" can NPU be compared to the rest??? There are some tidbits about MTL issues which I hope would be address before shipping...

LNL packaging is way more simple and elegant...When Intel announced 5 nodes in 4 years, we know Intel is focused on CPU IP thus the rest of SoC is based on TSMC process. And all roads lead to 18A process, my question is does the 18A's PDK include GPU IP???
Tiles based packaging is surely not cost effective, but actually more power efficient. N6 for SoC tile is definitely a hold back, but it's a lot cheaper i think. I remember reading somewhere that N6 is cheaper than Intel 7 even. Not sure though.

And 18A is a fat node. Has the full suite of cell libraries for all types of customers including ARM designs. No news about UHD or the hybrid HP-HD yet. We can expect Panther Lake to use the standard HP library & Pat recently mentioned they've hit PDK 0.9 which is a key milestone (meaning it's mostly finalized). Panther Lake tape-in may happen sooner than we think.
 

SiliconFly

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Rumor is that PTL is going to combine the CPU and SOC tiles but leave the GPU tile separate.
That doesn't sound right. The SoC tile takes up too much die space by itself. And has way too many modules that don't really need 18A which will drive up the cost of the tile significantly. Combining the SoC tile with the CPU tile will make the PTL cpu tile (on 18A) way too big & expensive and not worthwhile.

It's a lot easier combine the SoC tile & the I/O tile and move them to N5. Makes more sense in terms of efficiency, performance & cost. But combining the SoC & CPU tiles on 18A is a recipe for disaster.
 
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Starjack

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I'll be more curious to find out what how Intel will compensate for the Compute Tile size, especially since they will eventually add or subtract P/E cores. The current design i see in the die image on top looks like it supports 6 P-cores and 4 or 8 E-cores. Well you know they ain't gonna use that design right through for other models of their chips.
 

Tigerick

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That doesn't sound right. The SoC tile takes up too much die space by itself. And has way too many modules that don't really need 18A which will drive up the cost of the tile significantly. Combining the SoC tile with the CPU tile will make the PTL cpu tile (on 18A) way too big & expensive and not worthwhile.

It's a lot easier combine the SoC tile & the I/O tile and move them to N5. Makes more sense in terms of efficiency, performance & cost. But combining the SoC & CPU tiles on 18A is a recipe for disaster.
Actually, it is kind of makes sense. According to SA, die size of MTL's CPU tile is pretty small @ ~40 mm2. With 18A, CPU + IOD integration seems way to go especially if you can reuse tGPU from ArrowLake which is GT3 made by TSMC's N3E process.

AMD's Sarlak is combining GPU + IOD which is going to be made by TSMC's N3E. Intel's solution is opposite of AMD, well then it makes perfect sense :p
 
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Khato

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Intel was heavily focused on monolithic to avoid the pitfalls of power/performance/cost penalties introduced by chiplets. Even though they had the technology & even some chplet products like i7-8809G & Lakefield, they never bothered about the advantages of using chiplets until it was too late and AMD took the lead.
Heh, you can go back quite a bit earlier than Kabylake-G and Lakefield. Intel's first 'true chiplet' product was Clarkdale/Arrandale in 2010.
 
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SiliconFly

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Actually, it is kind of makes sense. According to SA, die size of MTL's CPU tile is pretty small @ ~40 mm2. With 18A, CPU + IOD integration seems way to go especially if you can reuse tGPU from ArrowLake which is GT3 made by TSMC's N3E process.

AMD's Sarlak is combining GPU + IOD which is going to be made by TSMC's N3E. Intel's solution is opposite of AMD, well then it makes perfect sense :p
Even better, Intel should just combine the CPU, SoC, I/O & GPU tiles and call it a day!
 
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SiliconFly

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I'll be more curious to find out what how Intel will compensate for the Compute Tile size, especially since they will eventually add or subtract P/E cores. The current design i see in the die image on top looks like it supports 6 P-cores and 4 or 8 E-cores. Well you know they ain't gonna use that design right through for other models of their chips.
I think power consumption & die size (and hence yield/cost) are the main limiting factors when adding more cores to the cpu tile. They also might have to switch out ring bus as it may become a limiting factor as well.
 

cebri1

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I don't believe this has been shared. Nothing really new, but basically:
  • Do not expect Redwood Cove (called "largely a port from the previous node core") to bring any significant IPC gains (the only ones may come from a larger L2 cache). The chip is primarily oriented at improving efficiency so we should expect a nice battery improvement due to core optimizations + Intel 4.
  • E-Cores does have a nice IPC increase (6-7% *4-6% according to @mikk* rumored), so MT workloads that use the e-cores should have better performance vs Raptor Lake at ISO frequencies.
  • Display Engine has some optimizations (PSR) to reduce the display power consumption.
  • They expect MTL iGPU to be the best performing iGPU in the market.
 
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DAPUNISHER

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I don't believe this has been shared. Nothing really new, but basically:
  • Do not expect Redwood Cove (called "largely a port from the previous node core") to bring any significant IPC gains (the only ones may come from a larger L2 cache). The chip is primarily oriented at improving efficiency so we should expect a nice battery improvement due to core optimizations + Intel 4.
  • E-Cores does have a nice IPC increase (6-7% *4-6% according to @mikk* rumored), so MT workloads that use the e-cores should have better performance vs Raptor Lake at ISO frequencies.
  • Display Engine has some optimizations (PSR) to reduce the display power consumption.
  • They expect MTL iGPU to be the best performing iGPU in the market.
I shared it on the last page, but never hurts for visibility. This thread is huge after all. You also did a great TLDW so well done :beercheers:

PC rag did a Q&A with Tim Wilson SoC design lead - https://www.pcmag.com/news/chiplet-chat-qa-with-intels-tim-wilson-soc-design-head-for-meteor-lake?
 

mikk

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When asked about Meteor Lake desktop Michelle Johnston Holthaus says it comes in 2024. I'm not so convinced she is correct though.

 

inf64

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RWC IPC about the same and Crestmont 4-6% better IPC in average, this is what Intel said. Redwood Cove in Granite Rapids seems different.
Anyone remembers this MLID "leak"?

"
We are being teased with 15-21% increases in IPC performance with the new Redwood Cove architecture over the Raptor Cove architecture, but with MLID apologizing for the huge range (15-21%) but I think that's fine."

No biggie, MLID missed it will be 0-1% , just a 100% failed prediction. I posted this here just to show how this guy either :
1) has no real sources
2) is making it all up for clicks and
3) has multiple "sources" who are actually trolls and who feed him BS info all the time
 

Geddagod

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When asked about Meteor Lake desktop Michelle Johnston Holthaus says it comes in 2024. I'm not so convinced she is correct though.

Oh ye that was also implied in the interview (that MTL desktop was coming). Filling out the lower end of the ARL lineup in desktop with MTL chips wouldn't be too unexpected tbh, but again, who knows.
 

Abwx

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Anyone remembers this MLID "leak"?

"
We are being teased with 15-21% increases in IPC performance with the new Redwood Cove architecture over the Raptor Cove architecture, but with MLID apologizing for the huge range (15-21%) but I think that's fine."

No biggie, MLID missed it will be 0-1% , just a 100% failed prediction. I posted this here just to show how this guy either :
1) has no real sources
2) is making it all up for clicks and
3) has multiple "sources" who are actually trolls and who feed him BS info all the time

He receive some noise but it look like he has trouble making the difference between IPC, frequency, better perf/watt that allow MT frequencies uplifts and so on, otherwise his 20% number is not far from other leaks, he s just unable to point to what parameter it is exactly related.