Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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PantherLake.png

LNL.png

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E2CPU + IOD + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake

INTEL-CORE-100-ULTRA-METEOR-LAKE-OFFCIAL-SLIDE-2.jpg

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

Clockspeed.png
 
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JoeRambo

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Edit: Why exactly is it more valid to test at JEDEC memory speeds again? Who’s buying a 7950X and 13900K and running JEDEC DDR5-4800?

It is only valid if JEDEC memory speeds are combined with JEDEC memory latency and sane, JEDEC defaults for other timings. Anandtech used to do this, and it was great even for enthusiast like me to provide baseline performance without memory tuning.

Other reviewers use various intellectually dishonest settings like:

1) "We test JEDEC speeds" and proceed to test at 5200CL32 for one vendor and 5600CL38 for other, subtle, but gives more advantage at 5200'ish speeds.
2) "We test at carbon copy timings and settings for both vendors" and proceed to test @ 6000CL32 when in fact it is edge of what is possible on vendor A at early maturity of platform and vendor B would happily run some 7400+ speeds with same effort involved.
3) Outright strange results for one vendor or another, where the rest of the web doesn't agree with them or their 'ordering' within vendor or between them. These "results" are great boon to certain faction warriors here.

For (3) it could be simply motherboards training, BIOS pecularities etc. Or sometimes even unscrupulous messing with secondary and tertiary timings. There are ways to boost and lower performance in trivial and more sophisticated ways, i think i'd easily manage to make FPS in some more sensitive game change +-10% with just tRFC and tREFI set "properly".
 
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FangBLade

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On the bright side high prices suggest confidence in its performance, right? :)
The MTL design is quite expensive to produce, significantly more costly than AMD's. Since this is their first chiplet design, it probably won't bring advancements in performance, and that's why they have focused exclusively on laptops, as a testing platform for this new design. It's very likely to bring improvements only in efficiency and graphics performance due to the Arc architecture. However, concerning the CPU part, I don't believe it will bring progress compared to RPL, where you can significantly increase the clock speed, and being a monolithic design means lower latencies (at least when communicating between P cores). AMD has been perfecting its chiplet design for years. Intel has many more resources, but no matter how many they have, I doubt they can make a significant leap with their first design. Arrow Lake will probably be their first major leap.
 

yuri69

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AMD has been perfecting its chiplet design for years. Intel has many more resources, but no matter how many they have, I doubt they can make a significant leap with their first design. Arrow Lake will probably be their first major leap.
You can get the rationale behind the AMD's chiplets in various papers. The most descriptive one is titled "Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families".

The partitioning was decided back ~2015 when the analysis was done for Zen 2. The primary driver behind the chiplets was the need to offer sanely-expensive 8-64+c SKUs on a process close to the bleeding edge. The partitioning itself was additionally driven by bandwidth, signal reach, and tech cost. This way it seems AMD keeps using the same chplet scheme since Zen 2 thourgh Zen 5 with a bit later addition of X3D.

Looking at the number of Intel SKUs, they obviously react to completely different driving forces of their lineup.
 

Abwx

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Edit: Why exactly is it more valid to test at JEDEC memory speeds again? Who’s buying a 7950X and 13900K and running JEDEC DDR5-4800?

If you set both platforms to DDR5-6000 that already gives Zen 4 an advantage since RPL can run DDR5-6400 (realistically it can do DDR5-7200 stable in most cases) without issues.

You dont get it, stock mean DDR5200 for AMD and 5600 for Intel, that s how NBC or Computerbase did their tests.
 

H433x0n

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Mar 15, 2023
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AMD has been perfecting its chiplet design for years. Intel has many more resources, but no matter how many they have, I doubt they can make a significant leap with their first design. Arrow Lake will probably be their first major leap.
In what way does the Ryzen chiplet configuration outperform Foveros?

Latency? No.
Energy Efficiency? No (2 pJ/bit vs 0.3 pJ/bit)
Bandwidth? No.
Cost? Yes.

I’d gladly pay more for a more performant system. There’s a reason why AMD uses monolithic designs for mobile chips and why Strix Halo and Zen 6 are going for 2.5D packaging.
 
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lightisgood

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In what way does the Ryzen chiplet configuration outperform Foveros?

Latency? No.
Energy Efficiency? No (2 pJ/bit vs 0.3 pJ/bit)
Bandwidth? No.
Cost? Yes.

I’d gladly pay more for a more performant system. There’s a reason why AMD uses monolithic designs for mobile chips and why Strix Halo and Zen 6 are going for 2.5D packaging.

Yes.
Intel adopted chiplet design and got to quad core as "Core 2 Quad" earlier than AMD.
However, Intel returned to monolithic for performance.
History roughly repeats itself.
 

lightisgood

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Core2 quad was not a chiplet design.

"Chiplet" is marchitecture. This is similar to Intel calling SMT as HTT.
C2Q attained time to market because it was designed by reused IP.
Yes, C2Q's contribution is similar to "Chiplet" Ryzen's.

P.S.
IBM, they never called thier POWER5 design as "Chiplet".
Again, "Chiplet" is handy word, however, this is marchitecture.
 
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Hitman928

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"Chiplet" is marchitecture. This is similar to Intel calling SMT as HTT.
C2Q attained time to market because it was designed by reused IP.
Yes, C2Q's contribution is similar to "Chiplet" Ryzen's.

P.S.
IBM, they never called thier POWER5 design as "Chiplet".
Again, "Chiplet" is handy word, however, this is marchitecture.

MCM isn’t the same as chiplets.
 

Hulk

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I have finally absorbed all of the information released regarding Meteor Lake. I have to admit there is a lot of cool technology going on here although AMD seems to have "gotten there" years ago with much of it.

That being said if "generational improvements" in IPC mean a few percent increase over Raptor Cove and Gracemont in the tiled configuration then that's pretty good for a first effort with so many "firsts" going on for Intel with this part.

Another "if" is if Intel's claim of 40% better efficiency at ISO power is true then a 6+8 Meteor will be a much better option over a 6+8 Raptor for mobile, especially considering Raptor can shut down the Graphics Tile.

Anyone know what process node will be used for the I/O tile?
 

aigomorla

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Normally we don't allow linking without comments.
Sometimes I will let it go depending on the content.

But what are you implying with this? That you used a Buzzword, or is this an attempt at some lost form of sarcasm.

Id advise if its the later, you will need to a comment, if its a blanket form of sarcasm, one where 95% of the viewers will understand, I will let it go.

Moderator Aigo
 

eek2121

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Aug 2, 2005
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wtf....



These below were what I knew before, but I never expect situation could be this bad.







also I just heard those weibo guys slams MTL power consumption isn't lower even a bit and buggy. I don't know what would happen now and I would still keep conservative about MTL perf.
We will see what happens at launch. These are premium chips, Intel is labeling them as such, and they cost quite a bit more than Raptor Lake Refresh chips.

A $1,500 2 lb laptop that can game moderately well (possibly even on battery)would be an insta-buy for me.
I’m not even going to bother with this


Yeah, frequency matters and ARL frequency seems like it’s going to regress much more than Zen 4 -> Zen 5. It’s a bummer for sure.
Knowing Intel, there won’t be a frequency regression, except maybe compared to the 14900k.
It is only valid if JEDEC memory speeds are combined with JEDEC memory latency and sane, JEDEC defaults for other timings. Anandtech used to do this, and it was great even for enthusiast like me to provide baseline performance without memory tuning.

Other reviewers use various intellectually dishonest settings like:

1) "We test JEDEC speeds" and proceed to test at 5200CL32 for one vendor and 5600CL38 for other, subtle, but gives more advantage at 5200'ish speeds.
2) "We test at carbon copy timings and settings for both vendors" and proceed to test @ 6000CL32 when in fact it is edge of what is possible on vendor A at early maturity of platform and vendor B would happily run some 7400+ speeds with same effort involved.
3) Outright strange results for one vendor or another, where the rest of the web doesn't agree with them or their 'ordering' within vendor or between them. These "results" are great boon to certain faction warriors here.

For (3) it could be simply motherboards training, BIOS pecularities etc. Or sometimes even unscrupulous messing with secondary and tertiary timings. There are ways to boost and lower performance in trivial and more sophisticated ways, i think i'd easily manage to make FPS in some more sensitive game change +-10% with just tRFC and tREFI set "properly".
This. A good reviewer should be running the system at stock to show baseline performance. Some reviewers do both, JEDEC and with optimized settings.

Many laptops and OEM desktops won’t let you touch timings as well. DIY is inly one piece of a larger pie.
 

Hulk

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Oct 9, 1999
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Like what?


It’s TSMC N6.
"Cool" is of course subjective but I think the following is cool:
Foveros 2nd gen interposer with 36u bump pitch, doubling data density from 1st gen.
The tiled approach allowing nodes to be tuned for each tile. ie CPU vs Graphics vs I/O.
E's on the SoC using a lower v/f curve process allowing them to power down to very low power levels along with display circuitry on the SoC allowing for the possibility of both the CPU and Graphics tile to power down under low loads and the computer to run solely on the SoC tile (with I/O of course).
128GB/sec scalable fabric/NOC on the SoC communication with the other tiles.
Neural processing unit on the SoC.
Claimed 40% power reduction at ISO frequency vs previous node.
 

DAPUNISHER

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Hitman928

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Whether it's Core 2 Quad, tiles or chips, it's all MCM under various marketing names that describe certain solutions.

So are you arguing that there is no reason to specify between different solutions with completely different approaches and technology? If this is the argument, why don't we just call all CPUs, GPUs, NPUs, etc., just processors? I mean, they all just do the same thing generically speaking, right? No reason to distinguish between them.

Chiplets denotes technically distinguishable features. Whether it has become somewhat of a buzzword doesn't mean it's not a legitimate industry term.

 
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lightisgood

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So are you arguing that there is no reason to specify between different solutions with completely different approaches and technology? If this is the argument, why don't we just call all CPUs, GPUs, NPUs, etc., just processors? I mean, they all just do the same thing generically speaking, right? No reason to distinguish between them.

Chiplets denotes technically distinguishable features. Whether it has become somewhat of a buzzword doesn't mean it's not a legitimate industry term.


And ? Does Ryzen use UCIe ?
(Yes, this is fault-finding. But, I think you are also doing this too.)

You said that Ryzen is chiplet, C2Q is not.
Surely, both product are different.
However, does your being fussy about "ONLY Ryzen is chiplet" have any meaning in this talk/thread ?
Did you read and understand what I & H433x0n wrote ?
 

Hitman928

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And ? Does Ryzen use UCIe ?
(Yes, this is fault-finding. But, I think you are also doing this too.)

You said that Ryzen is chiplet, C2Q is not.
Surely, both product are different.
However, does your being fussy about "ONLY Ryzen is chiplet" have any meaning in this talk/thread ?
Did you read and understand what I & H433x0n wrote ?

I never said Ryzen uses UCIe, but it does use chiplets. I linked to the website to show that the term is not just a buzzword but has been adopted as an industry term with actual technical meaning. I also never said that only Ryzen is chiplet, just that C2Q wasn't chiplet, which it wasn't. I did read what you posted and the post you quoted. I understand your point about Intel getting an advantage in TTM by doing an MCM and relating that to Ryzen, but even that really isn't the same situation between the two but I wasn't even going to debate about that and didn't care to. I was only pointing out that what you said wasn't exactly true as C2Q didn't use a chiplet type design because there are technical distinguishments between a classic MCM and a chiplet. Not sure why you seem to be so defensive over a small but factual correction.
 

lightisgood

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May 27, 2022
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I never said Ryzen uses UCIe, but it does use chiplets. I linked to the website to show that the term is not just a buzzword but has been adopted as an industry term with actual technical meaning. I also never said that only Ryzen is chiplet, just that C2Q wasn't chiplet, which it wasn't. I did read what you posted and the post you quoted. I understand your point about Intel getting an advantage in TTM by doing an MCM and relating that to Ryzen, but even that really isn't the same situation between the two but I wasn't even going to debate about that and didn't care to. I was only pointing out that what you said wasn't exactly true as C2Q didn't use a chiplet type design because there are technical distinguishments between a classic MCM and a chiplet. Not sure why you seem to be so defensive over a small but factual correction.

Okay, I'd like to accept your revisionism.
This boring, meaningless topic is the end here.
 

SiliconFly

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Mar 10, 2023
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MCM isn’t the same as chiplets.
Actually, chiplets is an umbrella term used to denote many type of packaging. For example. Infinity Fabric based MCM (AMD), Interposer based Foveros (Intel), older EMIB bridges (Intel) are all now known as chiplets.

Just for info, another interesting thing is, contrary to popular belief, Intel came out with chiplet-based CPU i7-8000 series CPUs 1.5 years before AMD. It was a Kaby Lake CPU tile & a Vega GPU tile on substrate linked by a EMIB bridge. But it was never mainstream. Two years later Intel came out with another chiplet-based CPU Lakefield, but that too wasn't mainstream. MTL is.

(See: link, types, AT 8809, Intel Ark, zen 2 release)
 

SiliconFly

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Mar 10, 2023
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Yes.
Intel adopted chiplet design and got to quad core as "Core 2 Quad" earlier than AMD.
However, Intel returned to monolithic for performance.
History roughly repeats itself.
Intel was heavily focused on monolithic to avoid the pitfalls of power/performance/cost penalties introduced by chiplets. Even though they had the technology & even some chplet products like i7-8809G & Lakefield, they never bothered about the advantages of using chiplets until it was too late and AMD took the lead.

Thats what happens when paper-pushing idiots are made to sit in the driver seat! Intel is a technology compang and should be run by engineers, not by bean-counting monkeys! Lesson learnt.
 

Hitman928

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Apr 15, 2012
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Actually, chiplets is an umbrella term used to denote many type of packaging. For example. Infinity Fabric based MCM (AMD), Interposer based Foveros (Intel), older EMIB bridges (Intel) are all now known as chiplets.

Just for info, another interesting thing is, contrary to popular belief, Intel came out with chiplet-based CPU i7-8000 series CPUs 1.5 years before AMD. It was a Kaby Lake CPU tile & a Vega GPU tile on substrate linked by a EMIB bridge. But it was never mainstream. Two years later Intel came out with another chiplet-based CPU Lakefield, but that too wasn't mainstream. MTL is.

(See: link, types, AT 8809, Intel Ark, zen 2 release)

Yes, there are multiple ways of producing a chiplet solution through various packaging technologies. They all have things in common though that the original C2Q didn't. I would also argue that Kaby Lake -G really wasn't a chiplet solution (though I could see an argument that it was) but Lakefield certainly was.
 
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