Question Intel had a 7 GHz CPU years ago

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Insert_Nickname

Diamond Member
May 6, 2012
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You can do date ranges, site specific, remove words or phrases in quoations, search body text, caption text, title texts. think of search as a method to search individual areas of a web page from the title to the date to the body text. the link you posted are 20 commonly known and easy methods. There are far more.

The google-fu is strong with this one. :D
 
Jul 27, 2020
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Northwood built with 18A, integrated memory controller with support for DDR5-10000, MTL tGPU/NPU, AVX10 and 6 GHz frequency. Man oh man, that would sure make a very nostalgic CPU for the old timers.
 
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Thibsie

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Apr 25, 2017
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Northwood built with 18A, integrated memory controller with support for DDR5-10000, MTL tGPU/NPU, AVX10 and 6 GHz frequency. Man oh man, that would sure make a very nostalgic CPU for the old timers.
Well, I'm still convinced that porting Northwood and modifying it would have been smarter than Prescott total failure (IMO).
 
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NTMBK

Lifer
Nov 14, 2011
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Northwood built with 18A, integrated memory controller with support for DDR5-10000, MTL tGPU/NPU, AVX10 and 6 GHz frequency. Man oh man, that would sure make a very nostalgic CPU for the old timers.
Was it really worth the thread necro for that?!
 

Mopetar

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Jan 31, 2011
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Was it really worth the thread necro for that?!

I was posting in a different thread the other day about frequency scaling and had been talking about how we could probably get a 10 GHz CPU today if it had a ridiculous pipeline. I had actually assumed it was related to that or it reminded someone of this thread.
 

NostaSeronx

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Sep 18, 2011
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With the information I have gotten so far. It is more likely that we get a 12FDX chip from AMD with a K9-ified Zen [Essential] core. Than, to get a Netburst core from Intel on 18A. Especially, with AMD's style of performance.Efficiency core combos.

Dali/Raven2 (2x 3.5 GHz :: single-point core implementation) to 12FDX SoC (2x two-point/[bare minimum improvement] core implementation):
Performance Core​
Efficiency Core​
>5.6 GHz​
>3.5 GHz​

Before, it was modified the AMD/GloFo NPI group, 2020+ seems to hint at a hexa-core chiplet: 2P+4E on 12FDX.

The above numbers are bare minimum. Essentially, a shrink from 14LPP/12LP @ 10.5T/9T to 12FDX @ 7.5T. One core takes the first-given frequency macro cell path, while the other takes first-given power/area macro cell path.

Simple first-given Perf core => ~5.6 GHz
Extra work not-first-given Perf core => ~6.9 GHz (~2x faster from Efficiency-variant is good.)

Which would give AMD an edge over this:
hacked6cto2c.png

FDSOI = Low Drag&&Friction FEOL
FinFET = High Drag&&Friction FEOL => 10x harder to get processors into Freq-max range.
GAA = Extremely High Drag&&Friction FEOL => 100x harder to get processors into Freq-max range.

Having >6 GHz is only feasible on FDSOI: https://pc.watch.impress.co.jp/docs/2006/0119/kaigai233_01l.gif

Single-core of an Updated Gen1 Zen @ ~7 GHz is about the equivalent of four old Zen cores running at ~3.5 GHz. Where a ~5.6 GHz updated core can replace two old cores at ~4 GHz or four cores at ~2.9 GHz.

Essential/Low-end workloads are more held-back by fixed problem size(more clock friendly). While more mid-to-high-end workloads are held back by fixed time amount(more core friendly).
 
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aigomorla

CPU, Cases&Cooling Mod PC Gaming Mod Elite Member
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Sep 28, 2005
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Northwood built with 18A, integrated memory controller with support for DDR5-10000, MTL tGPU/NPU, AVX10 and 6 GHz frequency. Man oh man, that would sure make a very nostalgic CPU for the old timers.

Have enough of them, and you can melt the entire polar ice caps just trying hack SHA256 encryption.
You do know the other name for those cpu's were gaming space heaters.
 
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Jul 27, 2020
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Tejas lets out a wail from its grave, "You murderers! I could have reached 10 GHz first! Each and every one of you will pay for canning me! I will be avenged!"

It is the curse of Tejas that put Intel in its current predicament. They really should go back and modernize Tejas for a modern node. Until they do that, they will keep running into hurdles. An unjust deed never goes unpunished.
 

NostaSeronx

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Sep 18, 2011
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It is the curse of Tejas that put Intel in its current predicament. They really should go back and modernize Tejas for a modern node. Until they do that, they will keep running into hurdles. An unjust deed never goes unpunished.
They will probably have to fab at GlobalFoundries. Modified it from the research papers regarding heat on high-performance GAA/Shrinked BOX FDSOI:
fdsoishe.png
Consider it a range(12FDX actual might be between 22FDX/12FDX and GAA between FinFET/GAA), also made it in like 5 seconds, so pardon the weird GAA tail/head angle and 12FDX tail being higher than 22FDX.

12FDX tensile Si NFET+compressive SiGe PFET and BOX=15nm(eSoC3) and lower BOX=10nm(eSoC3+).

I expect only RISC-V cores will push speeddemon to get around high-cost per-density FinFETs/GAA. Which immediately cuts out Intel since they will want x86.

Can take a scalar-core with RISC-V to 10 GHz to 20 GHz and it would still be viable against density-focused Fin/GAA.
2x 64-bit ALUs
2x 64-bit AGUs
2x 64-bit FPUs (non-SIMD)

Low-cost speed demon = dual-core replacing four-core/eight-core designs // 8-core tablets that are just a slow in-order cores or anemic OoO+many InO.
High-cost speed demon = octo-core replacing 32-core/64-core designs. // 64-core E2/E-next products that are relatively slow, where the market is FAST transaction rates.

Investment into Speeddemon architectures are only viable if there is big leaps in memory throughput.
RAM:
DDR2/DDR3/DDR4 DIMM, low speed delta
LPDDR5/LPDDR6/+ LPCAMM, high speed delta

Read mostly memory:
HDD/Slow Flash SATA, low speed delta
PCIe5/PCIe6/+ SLC+xLC low-latency/high-throughput NVMe, high speed delta

There is also Nantero's NRAM that can be used in RAM/RMM. What they are showing to the USG is pretty fast. Of, this I doubt Europe or Singapore would bother with Ultra-High-Freq. So, it would largely be up to Fab8 getting cheap 300mm FDSOI (from pasir ris) to get 12FDX out. In which, USG can fund these crazy speeddemon nutjobs with a science act.
fdsoicost.png FY25 = Late 2024

In short:
FinFET -> GAA -> Complementary GAA => High Density/High IPC preference for high performance.
FDSOI -> Planar Gate-semi-around -> Wafer M3D PGSA => High Speed/Mid IPC preference for high performance.

Coming out with a design that continues this trend requires FDSOI. It is unlikely to occur with FinFET/GAA/CGAA:
freqscale.png

Last major work, with Pentium 4-esque design had 15 GHz in target.
[3] = "A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit"
65nmhighfrequency.jpeg

Also, while the CPU is at https://valid.x86.fr/show_oc.php?id=2676347 , 8352.86 MHz (334.11 * 25) isn't the Fast ALUs in the Integer Core running double? [16705.72 MHz]
Almost every aspect of the Integer core is 2x processor clock. Ex: "The 144-entry 6r3w register file (Fig. 5.7.6) uses the 2× frequency clock to obtain a throughput of 12r6w per processor clock."

Before 65-nm Intel Pentium 4 came out in IEEE 2006 came out rewind to TeraHertz/"Pentium 5" target node 2002:
2002.png

The people who need to know do know. A true proper Tejas can only be on a FDSOI node.

Some delicious quotes:
"Intel denied that it's behind its rivals, claiming that it will skip traditional SOI and move to a next-generation technology called “thin SOI” or fully-depleted SOI"
"We expect to fully deploy the TeraHertz transistor by the second half of this decade. - Intel"
 
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Hulk

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Prediction based on extrapolation of clocks over the last 10-15 years.

We will not see 7GHz until 2026-2027 time frame.
 
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NostaSeronx

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Sep 18, 2011
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They could always port Prescott to Intel 4. Pentium 4 on Intel 4? What could possibly go wrong?
Well the more likely case of porting would be Cedar Mill to at least Intel 16.

1994 P54C .6μm BiCMOS -> 2012 Claremont 32nm -> 2013 Lakemont 32nm
1994 -> 2012/2013 = 18/19 years respectively
2006 + 18/19 years = 2024/2025

Cedar Mill's generation of P4 is more future proof in regards to shrinking gate length (90/50 -> 65/35 -> xx/lower): https://ieeexplore.ieee.org/document/1419253
Same power: Prescott-gen 3.6 GHz, scales worse -> Cedarmill-gen 4.5 GHz, scales best.

Where using Intel 16 mitigates most risk of such a port. Like Claremont/Lakemont on 32nm which was mature at the time. It also has the bare minimum of fully depleted transistors at lowest cost, while not moving fabs.

It also has the benefit of not jumping far away from 35nm gate length:
intelnode.png
Of which, Intel's 22FFL/16 has the best scaling from Intel's 65nm(lg=35)/32nm(lg=30) nodes across the board. If anything a port down will be faster than Tejas goals and exceed power reduction of standard node non-L 65->45->32->22. In the 22FFL IEEE paper Intel indicates heavily that there will be a 14FFL/10FFL later on. Where they revisit those nodes and fix them like No Man's Sky, Cyberpunk 2077, Final Fantasy 14. 22FFL/Intel 16 is a sufficient pull back on relative merits to other FinFETs. Similar to 65nm PDSOI(Lg=35) Phenoms w/ max stock: 2.6 GHz to 45nm PDSOI(Lg=40) Phenom IIs w/ max stock: 3.7 GHz.

Where this product can probably base its iGPU on an improved HasVK physical implementation:

NetburstR (Intel 16) + Gen7.5R/(8R-backport?) (Intel 16) => lowest cost viable product at single vendor.

Should still be better than getting RISC-V/ARM minipcs and running Box64[-32] for backwards support. Compared to Micro Magic Inc's Quad-core(RISC-V) at 5.2 GHz at TSMC 16nm, it is likely NetburstR would be faster.
 
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SarahKerrigan

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Oct 12, 2014
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