I'm getting a strong feeling of lust for this CPU. 150W ain't that much. Imagine what this CPU could have been if it had been developed further, with modern branch predictors and huge caches.
Thunder 57
Diamond Member
- Aug 19, 2007
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That's the first I'm hearing of that. I don't buy it. How could Intel have a 64 bit version that was compatible with AMD's without AMD's design? For example, how would they know to add registers and how many? Are you sure you aren't mistaking 64 bit for hyperthreading?
yes our very own nostradamus.
Hey! I take offense to that. i had a P4 laptop. sure it burned your legs and very likely reduced your little soldier count over time but it wasn't that bad.
No, it doesn't. I still haven't been able to find my "moment of clarity" SOI interview. I think Google is now more tuned to return results in the recent past, rather than a decade or more ago.
Fanatical Meat
Lifer
- Feb 4, 2009
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Forum post summarizing what was said and it may have been the heat density is similar to a nuclear reactor.
Intel's CTO: "Pentium PC needs Nuclear Power!"
Intel's CTO: "Pentium PC May Need the Power of a Nuclear Reactor" Computer Chips to be Hotter than the Sun? by Anton Shilov 02/20/2004 | 06:27 PM Heat dissipation of the latest Intel processors, such as high end Pentium 4 and Pentium 4 E, has become a widely discussed issue. Reasons and consequen...
www.neowin.net
It wasn't compatible with AMD's. They had their own 64 bit x86 extension, and supposedly tried to get Microsoft to support it after Microsoft announced its support for AMD64. Microsoft basically told them to pound sand, that they would support only one 64 bit x86 extension and Intel had come to them too late.
Intel had a several year long internal fight about whether x86 should be extended to 64 bits. The x86 team thought it was only logical, the Itanium team and Intel's beancounters wanted x86 to remain 32 bit only and force everyone onto Itanium as the path forward to get 64 bits. Basically Itanium would eat the market from the top down, as different market segments needed 64 bits they'd be forced to make the move, and sometime in the following decade when 64 bits was all the way down to low end CPUs would have a legal patent protected monopoly since the only one able to make Itanium CPUs other than Intel was HP, who could only use it in their own hardware and couldn't sell the CPUs alone.
The x86 people apparently defined a 64 bit extension and built it into multiple generations of P4, but were not allowed to enable it (and of course had to scrap it and support AMD64 eventually) Maybe the thought was that if AMD challenged with their own then Intel could introduce their incompatible extensions and set AMD behind by years, but it turned out it worked the other way around.
http://www.chip-architect.org/news/2003_03_26_Prescott_clues_for_Yamhill.html
http://www.chip-architect.org/news/2003_04_20_Looking_at_Intels_Prescott_part2.html
They ran into something of a thermal wall at around 3.8GHz. Intel's engineers hadn't foreseen that. The P4 never did make it to 4GHz officially. But that's still 7.6GHz ALUs, so pretty respectable.
...and today we have an officially validated CPU with a 5.8GHz turbo. Isn't progress wonderful?
The P4 must have been a hit in your country. Turn off heating, start playing games or run a heavy DC workload and feel the radiating warmth and love from your dear P4. Intel loves you!
Gideon
Platinum Member
- Nov 27, 2007
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Well, AMD is the reason Intel couldn't force their nonsense architectures on us
IMO it has much more to do with the Core (2) architecture (that reached much higher performance even at measly 2.5-3.5 Ghz) rather than AMD.
Tejas was cancelled in May 2014 (after tapeout, so they knew the initial perfomance of it). The same month mobile Dothan chips were released that could reach 2.26 Ghz on 90nm process @ 27W TDP:
Intel® Core™ Processors, FPGAs, GPUs, Networking, Software
Browse Intel product information for Intel® Core™ processors, Intel® Xeon® processors, Intel® Arc™ graphics and more.
ark.intel.com
65nm Dothan (original Core Duo) was released in January 2006 and Conroe's Anandtech preview was published in March 2006. Here is a small recap:
In May 2005. This is how a dual-core 2.4 Ghz A64 X2 performed against a dual-core 3.2 Ghz Prescott (that was supposed to reach 6 Ghz) at a 25% clock deficit.
Full review
In April 2006, this is how a previewed Core 2 duo (Conroe) absolutely decimating the same A64 chip at rendering (at lower clock speed):
Link to preview
Finally here is The full review of Core 2 duo in July 2006.
Notice how Pentium needed 3.8 GHz to beat AMD at 2.8 GHz (35% higher clocks) in encoding. And encoding was the best case scenario for Pentium, as it had decent SSE support. Rendering and particularly gaming fared way worse (just see the review).
Against Conroe, Prescott (Simthfield) had 51% more IPC in this test. And again, that's Pentiums best case. In Cinebench 1T for instance Conroe had nearly twice the IPC (96% more!).
Oh, and btw, this is the gaming performance:
Now, 3.8 Ghz was the maximum actually squeezed out of Prescott (that was supposed to go to 6 Ghz) and it was a near brick-wall from there on. Conroe was sold up to 3.2 Ghz stock, but could also reach up to 4 GHz when overclocked.
So even a 7Ghz Prescott (let alone a newer even longer pipeline design) would not have outperformed a ~3.8Ghz Conroe in a lot of tasks. And 3.6-3.8 would definitely have been doable, had Intel had any competition.
As we mentioned Conroe didn't come out of the blue It was the direct successor of the Pentium M line already shipping since 2003 (Banias, Dothan ,Yonah). Considering how long validation takes, Intel definitely knew in 2004 the ballpark-performance of Dothan's successor's desktop version (Conroe). It would have been a no-brainer even if it never got past 3 GHz on it's first implementation.
TL;DR
Intel already had chips working in the lab, that could beat any of that 7Ghz design's reasonable performance estimates. That's why they cancelled it. Not due to anything AMD did.
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I was glad to trade in my P4 work PC for a Core 2 Duo. That P4 could affect room temperature to a certain extent running full tilt.
So the company probably saved a bit on heating.
None of those old CPUs have a patch on Alder/Raptor Lake however. Intel Space Heater edition.
At least the ADL/RPL BIOS have the option to limit power. Something I think was not possible with P4?
The ironic thing is they're pretty efficient if you run them at more reasonable power levels.
The only way I know you could keep a P4 down was downclocking and undervolting. The later variety (600-series I think) at least had SpeedStep for idle, but they were still power hungry. Cedar Mill was actually fairly well behaved, but by then C2D was out, and it was too little too late.
kschendel
Senior member
- Aug 1, 2018
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I guess it's arguable what exactly the root cause was, when there were multiples. I always saw the very long pipeline as being the primary bad guy, with tricks like the trace cache as being attempts to paper over the problems inherent in such a long pipeline.
No clue, but there are hints that the Pentium 4 team was quiet fired. They weren't allowed to fix glaring issues at all.
Both Prescott and Tejas were in planning to be IA-64/Itanium compatible-processors. However, both of generations of that were canned. Which lead to a exodus out of Intel of those stuck in the Pentium 4 team.
Single IA32 decode -> slow trace cache fill, more complex instruction re-ordering.
IA64 path -> fast trace cache fill, more simple instruction re-ordering.
Itanium's small L1 caches -> Pentium 4's small L1 caches. It was also hinted for this roadmapping since both Itanium and Netburst both had 128 Int Regs and 128 FP Regs. At the time(Willamette plus), it was a forgone conclusion that IA-64 would be embedded into Netburst.
The long pipeline isn't an issue if Intel actually built around it. Missing the trace cache meant accessing the L2 cache. Which made something long, even longer since the whole 20-stage pipeline thing only covered trace cache down. Not CISC instruction fetch down...
The trace cache wasn't a trick, but something technically needed.
TC => ~6 uops per session
3-wide decode => <1.5 uops per session.
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IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
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As I outlined above, the many pipeline stage was ONE reason it performed bad.
With a Trace Cache miss, Pentium 4 was an effective 1-wide CPU.
@igor_kavinski It's Nosta. Best to not take it seriously.
No offense and maybe I'm too naive, but his posts make him seem like an actual (retired?) silicon engineer. You do know that truth is stranger than fiction?
With the code out in the wild back then... the misprediction rate was ~10%. When it matter, the trace cache hitted so not having a fast L1 instruction cache is a muted problem. It however is an issue when the core needs to have low-access latency to get future instructions.
Trace cache is fine when branchy/integer code that can usually fit in trace cache in hot code.
Where switching applications or anything that goes Int <-> FP can usually flush the trace cache.
Problem would have been fixed in Prescott if Intel's management didn't quiet fire the team.
(did anyone else notice it said fletch?)Really want to iterate Willamette/Northwood were released unfinished because of delays. Then, Prescott was suppose to be a finished, complete product. Of which, IA-64 was suppose to be its primary feature being a massive overhaul over the broken ones.
Intel management:
Do your new architecture thing for Prescott.
Nope, now do your new architecture thing for Tejas. -> https://ieeexplore.ieee.org/document/1332640 (Forced to do a small improvement over Northwood)
- Intel employees leave
Nope, now do your new architecture thing for Nehalem. -> https://ieeexplore.ieee.org/document/4039605 (Forced to do a small improvement over Prescott)
- Intel employes leave 2.0
I am actually secretly quoting a couple Intel Engineers most of the time.... So. yeah. Google groups is definitely a thing where they dumped out grievances.
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IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
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No. You are a meanie to him. Be offended if you like but I say it like it is.No he's not lol. He's a comic relief of the forum. Everyone knows that.
What other operators are there, other than + and quotes that would help in refining the search?
Nothing useful here for my purposes: https://ahrefs.com/blog/google-advanced-search-operators/
You can do date ranges, site specific, remove words or phrases in quoations, search body text, caption text, title texts. think of search as a method to search individual areas of a web page from the title to the date to the body text. the link you posted are 20 commonly known and easy methods. There are far more.
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