Discussion Intel current and future Lakes & Rapids thread

[DavidC1]

If the P cores in GraniteRapids are physically different from the RedwoodCove cores in MeteorLake, they are certainly not RedwoodCove+.

It is Redwood Cove in the case that it doesn't get full changes. Code names are arbitrary definitions set by people and they can set it whatever they want you know? Again, refer back to Goldmont "Plus" as an example. Was that just a "Plus"?

Edit:
Intel had already made a mistake because, according to the slides, SunnyCove in Xeon has ROB 384, but the inquisitiveness of journalists forced Intel to react and it was officially admitted that it was a mistake, because SunnyCove in Xeon is the same as in IceLake and ROB is 352.

In the case of Granite Rapids it is backed up by Pat's statements that the move from Intel 4 to 3 and the time lag allowed it to squeeze in more changes and to quote: "10 plus percent improvements".

While it is one thing to mess up on numbers(they don't always make mistakes either), it is another thing to state "performance-efficiency" and "performance improvement in the core" and specific things like branch prediction and memory parallelism related improvements.

 

[csbin]

RWC on GNR just has a few more instruction sets (AVX10.1, AMX...

https://twitter.com/x/status/1790477798337085778

 

[static shock]

Arrow Lake will not disapoint anyone. Per the contrary...

 

[igor_kavinski]

Looks like an old thread on AnandTech about future Intel processors (Coffee Lake, Ice Lake) from back in 2017. Interesting to see what people were hoping for back then!

How will you read 900+ pages? Gonna AI summarize it?

 

[trivik12]

SO Granite rapids 1st cpu launch is going to be 128 core model. It would be good apples to apples comparison with Turin. Plus Intel 3 vs N4P for Turin.

 

[lightisgood]

SO Granite rapids 1st cpu launch is going to be 128 core model. It would be good apples to apples comparison with Turin. Plus Intel 3 vs N4P for Turin.

Intel is able to release Granite Rapids-AP as up to 144 cores product (e.g. SPR@60C).
However GNR-AP is actually up to 128 cores product and has >16 redundant cores.
This is clearly good sign, probably, GNR boasts of sufficient competitiveness.

 

[trivik12]

Plus all the accelerators are enabled by default across all Skus. Intel did absolutely stupid stuff in trying to make it optional and hoping for additional $. Enabling it for default would lead to wide spread adoption. On top of it the RWC+ core in GNR is different from RWC on MTL. It would be interesting to see the reviews.

 

[cebri1]

Intel Xeon 6780E / Xeon 6766E 144-Core Performance Benchmarks Review - Phoronix

www.phoronix.com

“The Xeon 6780E 2P was delivering slightly better performance than the Xeon 8592+ 2P at... 70% the power consumption on average. The generational uplift in power efficiency with the Xeon 6700E is significant. Or if still relying on Ice Lake era infrastructure, the geo mean performance from the Xeon Platinum 8380 2P flagship to the Xeon 6780E was 1.896x the performance at 73% the CPU power consumption!

One Xeon 6766E was also about 5% faster than a single Xeon Platinum 8592+ while the Sierra Forest CPU was consuming just 55% the power of the prior Emerald Rapids flagship.“

 

[AMDK11]

Do I see correctly? According to this slide, RedwoodCove has an 8-way decoder like LionCove? Is this a bug or what?

 

[Henry swagger]

Do I see correctly? According to this slide, RedwoodCove has an 8-way decoder like LionCove? Is this a bug or what?

Its redwood cove plus architecture

 

[AMDK11]

Its redwood cove plus architecture

So you think there are two versions: RedwoodCove with a 6-way decoder and RedwoodCove with an 8-way decoder?

It doesn't stick to me. This appears to be blocked additional features in MeteorLake. A wider decoder is a bigger change than + to RedwoodCove.

I don't buy it and think it's a bug or that it's the exact same cores but new instructions are blocked in Meteor.

It would be best to compare the shots of both cores.

 

[SiliconFly]

So you think there are two versions: RedwoodCove with a 6-way decoder and RedwoodCove with an 8-way decoder?

It doesn't stick to me. This appears to be blocked additional features in MeteorLake. A wider decoder is a bigger change than + to RedwoodCove.

I don't buy it and think it's a bug or that it's the exact same cores but new instructions are blocked in Meteor.

It would be best to compare the shots of both cores.

Same here. I don't buy it either. Frankly, Intel should stop allocating resources to RWC (or RWC+ or RWC++) & ditch it altogether, move the the team to DMR, and accelerate it's release. Instead of releasing outdated products that just DOA. GNR is too little too late.

 

[DavidC1]

Same here. I don't buy it either. Frankly, Intel should stop allocating resources to RWC (or RWC+ or RWC++) & ditch it altogether, move the the team to DMR, and accelerate it's release. Instead of releasing outdated products that just DOA. GNR is too little too late.

What do you guys mean by it doesn't make sense?

It backs up Pat's statements perfectly. Paraphrasing, "Because of the move to Intel 3 and moving back the timeline, we were able to fit more performance, ten-plus percent in the core".

This is exactly what it is. They are saying it and you are saying, no, no, no.

 

[trivik12]

Same here. I don't buy it either. Frankly, Intel should stop allocating resources to RWC (or RWC+ or RWC++) & ditch it altogether, move the the team to DMR, and accelerate it's release. Instead of releasing outdated products that just DOA. GNR is too little too late.

We have not seen any reviews and already you are calling it DOA !!! Wait until Intel On event. You will see reviews. I expect 3rd reviews like from phoronix and others on Day 1 similar to SRF.

 

[SiliconFly]

We have not seen any reviews and already you are calling it DOA !!! Wait until Intel On event. You will see reviews. I expect 3rd reviews like from phoronix and others on Day 1 similar to SRF.

It's just that I'm not a big fan of RWC. I strongly feel a fat/power-hungry uarch like RWC shouldn't exist in this day and age. LNC is the right way to go. Good performance & better efficiency.

And most importantly, I can't wait for CWF with it's 288 darkmont cores. I'm pretty sure it'll be extermely powerful and efficient enough to blow the competition to smithereens.

 

[H433x0n]

Same here. I don't buy it either. Frankly, Intel should stop allocating resources to RWC (or RWC+ or RWC++) & ditch it altogether, move the the team to DMR, and accelerate its release. Instead of releasing outdated products that just DOA. GNR is too little too late.

I wouldn’t jump to conclusions yet. Just 2 days ago I would’ve called SRF DOA and yet the results were well beyond what we expected and somehow Xeon is the best defense against ARM’s encroaching market share in the data center.

GNR may end up being more competitive than you expect.

 

[SiliconFly]

GNR may end up being more competitive than you expect.

I want it to. But every cell in my body screams otherwise. And there's a distant voice that keeps saying "die RWC die".

 

[DrMrLordX]

Just 2 days ago I would’ve called SRF DOA and yet the results were well beyond what we expected

Eh??? What exactly did you expect from Sierra Forest?

 

[lightisgood]

I wouldn’t jump to conclusions yet. Just 2 days ago I would’ve called SRF DOA and yet the results were well beyond what we expected and somehow Xeon is the best defense against ARM’s encroaching market share in the data center.

GNR may end up being more competitive than you expect.

Based on SRF's review, it seems to be Intel at least fulfilled the PPW promise of Intel 3.
I'm sure that Xeon 6 has good competitiveness.
However, Intel DCAI's mainstream product is Emerald Rapids in this year, yet.

 

[Henry swagger]

https://twitter.com/x/status/1801284567673815288

Intel flexing on turin.. xeon 6900p will destroy it even more 😃😁

 

[Nothingness]

Intel complaining that the competition is not fair with the optimization of the software stack is ironic.

 

[Markfw]

https://twitter.com/x/status/1801284567673815288

Intel flexing on turin.. xeon 6900p will destroy it even more 😃😁

So they used custom software and a total of 3 processors to barely eeek out a win, instead of generic software, where it was crushed. I would not say Turin was destroyed, but the other way around.

 

[lightisgood]

https://twitter.com/x/status/1801284567673815288

Intel flexing on turin.. xeon 6900p will destroy it even more 😃😁

Yes. This is typical Lisa's AMD.
Lisa had an advantage over Krzanich, however, today's intel is Pat's intel.

AMD says that MI300 is wonderful and is refusing to submit MLPerf results as if running away.
Meanwhile, Intel confirms to submit Gaudi3's MLPerf results at the almost same time as launching product.

Also see this...

AMD MI300X Up To 3x Faster Than NVIDIA H100 In LLM Inference AI Benchmarks, Offers Competitive Pricing Too

Tensorwave has published the benchmarks of the AMD MI300X in LLM Inference AI workloads, offering 3x higher performance than NVIDIA H100.

wccftech.com

P.S.
Paul Alcorn, famous Tom's hardware writer, reports this news, too.

Intel fires back at AMD's AI benchmarks, shares results claiming current-gen Xeon chips are faster at AI than AMD's next-gen 128-core EPYC Turin

The AI flame war heats up.

www.tomshardware.com

> Notably, Intel does submit its CPU and Gaudi test results
> to the publicly-available industry accepted MLPerf database
> to allow for easily verifiable AI benchmark results,
> whereas AMD has yet to submit any benchmarks for comparison.

 

[dullard]

So they used custom software and a total of 3 processors to barely eeek out a win, instead of generic software, where it was crushed. I would not say Turin was destroyed, but the other way around.

I don't understand your statement. Why do you think Intel used 3 processors in a 2 socket configuration?

Intel stated by using the open source PyTorch software you get 686 requests and by optimizing it you could turn off SNC to get 740 requests. This is compared to AMD's claim of 671 requests for their chip on an unspecified software/configuration. All on two 64 core Intel processors vs two 128 core AMD processors.

 

[Khato]

What exactly was the setup on the original AMD benchmark? Did they release a slide deck with the actual configurations used for the claims? Or could they have been using 'generic software' on Xeon and custom tuned non-public software on Turin to make it look better than it is?