It all depends on how much of an IPC increase LionCove achieves and how it compares to Zen 5. LionCove is supposed to be enough for 2 generations of LGA1851 processors and for the next generation of Xeon processors.
DrMrLordX
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How much of Sapphire Rapids' problems stem from the cores rather than the packaging/interconnect? Emerald Rapids was a decent (if belated) step forward. No, I don't think Granite Rapids will be good competition for Turin at all. But as a successor to Sapphire and Emerald Rapids, it should be quite a step forward, at least in terms of efficiency.
adroc_thurston
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Plenty, part still has horrible PPA even in its MCC incarnation (34c at 700mm^2 die is nasty).
DrMrLordX
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Didn't Emerald Rapids partially solve that problem? The performance wasn't stellar but perf/watt was improved. It was just too late and was never going to be competitive with Genoa.
adroc_thurston
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No, but it did DTCO the living hell out of LLC.
It better do. but again, I'm talking MCC, which is ~unchanged for EMR.
SPR-XCC is a really special, really funny case of Bad.
Intel's HBM ploy didn't work out either. I think they really have a culture of "let's brute force this first and think later!".
adroc_thurston
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yeah not news, TACC posted SPR-HBM findings awhile ago.
Intel's HBM ploy didn't work out either. I think they really have a culture of "let's brute force this first and think later!".
It was bad. real bad.
branch_suggestion
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The evolution of single-core bandwidth in multicore systems — update
I keep telling Intel, go back to using eDRAM!!!
It's probably better than whatever crap they have going on currently in their server CPUs.
branch_suggestion
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The issue is their mesh and uncore being all sorts of woeful.The evolution of single-core bandwidth in multicore systems — update
sites.utexas.edu
View attachment 99380
I keep telling Intel, go back to using eDRAM!!!
It's probably better than whatever crap they have going on currently in their server CPUs.
Almost 3 years ago we had this leak. Looks like Arrow Lake was delayed (so Raptor Lake Refresh). But removing the delays Intel is following this leak.
DrMrLordX
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Arrow Lake was always going to face off against Zen5. Unless Intel pulls a major coup, it's not going to "reach parity" as projected. Also the Lunar Lake performance projection seems a bit rosy.
The RWC in Granite Rapids is not exactly the same core as the one in client, but an enhanced one with improved branch prediction and memory parallelism capabilities.
Pat said 10-plus percent. This is just like the E cores where Sierra Glen has no changes uarch wise but Crestmont does. Another indicator is that the 80-core version has 40% improved performance at the same TDP level(thus 40% improved perf/W) over 64 core Emerald Rapids, so a lot of that gain is coming from other than clocks.
Also it'll be much more competitive than it is today, where Emerald Rapids slots firmly in the mid in terms of pricing.
5th Gen Intel Xeon Processors Emerald Rapids Resets Servers by Intel
We delve into the 5th Gen Intel Xeon Scalable Emerald Rapids generation and talk both the performance and platform gains around the new chips
I don't know what AMD plans to do about Zen 5 not having an NPU. Maybe they will release Zen 5 APUs to fulfill that need? But then, it won't be a direct competitor to Arrow Lake K series since the APUs don't approach the performance of X series AMD CPUs.
APUs are fine for it. DT Copilot + PC is a niche market and will be driven more by OEMs pushing it rather than actual demand.
The Z5 core jit killing performance is actually much more meaningful for business.
Nah man, if Lion Cove turns out to be faster than Venice, I am personally going to eat my hat.
The RWC in Granite Rapids is not exactly the same core as the one in client, but an enhanced one with improved branch prediction and memory parallelism capabilities.
Pat said 10-plus percent. This is just like the E cores where Sierra Glen has no changes uarch wise but Crestmont does. Another indicator is that the 80-core version has 40% improved performance at the same TDP level(thus 40% improved perf/W) over 64 core Emerald Rapids, so a lot of that gain is coming from other than clocks.
Also it'll be much more competitive than it is today, where Emerald Rapids slots firmly in the mid in terms of pricing.
5th Gen Intel Xeon Processors Emerald Rapids Resets Servers by Intel
We delve into the 5th Gen Intel Xeon Scalable Emerald Rapids generation and talk both the performance and platform gains around the new chipswww.servethehome.com
According to Geddagod it's the same as Crestmont in MTL: https://forums.anandtech.com/thread...ussion-threads.2606448/page-116#post-41078598
RedwoodCove in Xeon looks exactly the same as in MeteorLake. Intel just isn't bragging about the IPC improvements in Meteorlake because the first attempt at tiles killed the IPC growth. However, RedwoodCove in Xeon will benefit from an increase in IPC.
That's because Meteorlake's P core only has doubled L1I cache as an improvement.
P cores:
Meteorlake-
Granite Rapids:
On P cores it says "Improved performance efficiency" with zero mention of architectural additions on Meteorlake, while on Granite Rapids it says: "Improved Branch predictor and miss recovery, 3-cycle FP multiplication, More outstanding memory requests and prefetch capabilities". Those are actually significant changes.
E cores:
Meteorlake-
Sierra Forest-
E cores on Meteorlake gets the 6-wide allocate/rename while on Sierra Forest it remains at 5, same as Gracemont. It also specifically says "IPC gains" and "Enhanced branch predicton" on Crestmont, not on Sierra Glen.
In both cases of Sierra Glen and Meteorlake's P core "improved performance efficiency" or "improved efficiency" means in terms of perf/clock they got nothing to show for. It's an excuse to add another bullet point.
Stop parroting what most others believe and actually look for yourselves people. They tell you right there. They aren't recycling cores this generation.
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I know that. It seems strange that there would be two different architectures between GoldenCove and LionCove? I know these are unsubstantiated claims on my part, but I believe it's the same core. High resolution shots and comparison with MeteorLake should dispel doubts.
Perhaps it's because it appears that way in the slides, but I think it would be useful to examine and compare photos of the Xeon and MeteorLake arrays.
Overall it's weird that in MeteorLake they only add 64KB L1-I and call it RedwoodCove. So there is a different core architecture in Xeon and it is not RedwoodCove because in Xeon it would be completely different than RedwoodCove. Or it's the same thing, but it's definitely not RedwoodCove+.
It would be an even bigger disappointment if it turned out that ArrowLake does not use LionCove, but the P Core architecture from GraniteRapids.
Either way, there would be 2 modifications and expansions between GoldenCove and LionCove? Something doesn't feel right here. But that's just my opinion.
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It's under a different code-name because it's on a different process, even if only has a minor architectural change. Pat has said it's like a + for Granite Rapids. Penryn, Ivy Bridge, Broadwell, all had minimal changes, but different code names because it's on a new process.
RWC on Granite Rapids is obviously not Lion Cove, because it's not wide as Lion Cove is. But this makes sense and it fits with Pat's statement that the move to Intel 3 and a year delay allowed it to have additional changes. They weren't able to fit Lion Cove in there, but they were able to fit more than the client Redwood Cove.
Ultimately the names are not important and tells you little. They called it Goldmont Plus, but a significant gain of 30% per clock.
Die shots do not tell you everything, because Intel can choose to have it disabled. The Xeon differs in one aspect, which is having the 512-bit AVX512 unit, which the client does not have.
Opinion is one thing, but Intel is telling you right there, the core in Granite Rapids is different. I don't know why there are doubts? Opinions also said Intel was dead after Netburst and that AMD was dead after Bulldozer.
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If GraniteRapids has these changes and MeteorLake does not have them in P cores, then it is definitely not RedwoodCove+. And if the P cores have features enabled in GraniteRapids and disabled in Meteorlake, they are physically the same cores.
GraniteRapids has 2x512-bit AVX, as does GoldenCove with SapphireRapids-EmeraldRapids, and this is the physical difference between the P-cores in AlderLake and RaptorLake.
If the P cores in GraniteRapids are physically different from the RedwoodCove cores in MeteorLake, they are certainly not RedwoodCove+.
Edit:
Intel had already made a mistake because, according to the slides, SunnyCove in Xeon has ROB 384, but the inquisitiveness of journalists forced Intel to react and it was officially admitted that it was a mistake, because SunnyCove in Xeon is the same as in IceLake and ROB is 352.
There is one more issue. According to Intel's slide, SunnyCove with the IceLake-SP queue is 70 microops per thread (SMT) and 140 microops per single thread (ST). While the GoldenCove in the photo increased from 70 to 72/thread (SMT) and an increase from 70 to 144 per thread (ST). 100-point question: which version is true?
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Panino Manino
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