Discussion Intel current and future Lakes & Rapids thread

[Geddagod]

not totally unexpected. ~2.5 years before launch is when Intel says 1rst customer communication begins.

 

[coercitiv]

Turns out Sapphire Rapids was cheating a bit for a while, luckily Emerald Rapids is a fair player:

Industry group invalidates 2,600 official Intel CPU benchmarks — SPEC says the company's compiler used unfair optimizations to boost performance

It mostly affects Sapphire Rapids benchmarks.

www.tomshardware.com

SPEC says it will no longer be publishing SPEC CPU 2017 results for Intel CPUs running a specific version of the Intel compiler, citing displeasure over an apparent targeted optimization for a specific workload (via ServeTheHome and Phoronix) that essentially amounts to cheating. A note has been added to the more than 2,600 benchmark results published with the offending compiler, effectively invalidating those results, mostly from machines running 4th Gen Xeon Sapphire Rapids CPUs.

According to Phoronix, the optimization could boost performance in SPECint by 9% overall. The publication also notes that versions 2022.0 to 2023.0 of the Intel oneAPI Compiler are impacted, meaning most of the now-invalidated results were run in 2022, largely on Sapphire Rapids CPUs.

Results for fifth-gen Xeon Emerald Rapids CPUs are very unlikely to have been running a version of the compiler with the banned optimization since Emerald Rapids came out after the good versions of the compiler were available.

 

[DAPUNISHER]

Intel pulling the old "if you ain't cheating you ain't trying." 👎

 

[Dayman1225]

Intel Clearwater Forrest (successor to Sierra Forest) is rumoured to use 3D stacking and hybrid bonding aka Foveros Direct

https://x.com/squashbionic/status/1759631239563386952?

 

[tamz_msc]

New details of cache hierarchy on EMR from ISSCC:

https://twitter.com/x/status/1759709786915119194

 

[AMDK11]

Intel Xeon "Granite Rapids" Wafer Pictured—First Silicon Built on Intel 3

Feast your eyes on the first pictures of an Intel "Granite Rapids" Xeon processor wafer, courtesy of Andreas Schilling with HardwareLuxx.de. This is Intel's first commercial silicon built on the new Intel 3 foundry node, which is expected to be the company's final silicon fabrication node to...

www.techpowerup.com

The first clearer photos of the wafer with GraniteRapids chips on Intel 3.

You can see 33 cores (RedwoodCove) per chip.
4 rows of 7 cores and 1 row of 5 cores.

 

[Philste]

The first clearer photos of the wafer with GraniteRapids chips on Intel 3.

You can see 33 cores (RedwoodCove) per chip.

It's Emerald Rapids, as many pointed out below his Tweet. He corrected it now.

 

[AMDK11]

It's Emerald Rapids, as many pointed out below his Tweet. He corrected it now.

Thanks! Now I checked and remembered what the EmeraldRapids tile looks like and it is actually not GraniteRapids. Unfortunately, the news on Techpowerup still says it is GraniteRapids.

 

[Dayman1225]

Intel Clearwater Forrest (successor to Sierra Forest) is rumoured to use 3D stacking and hybrid bonding aka Foveros Direct

https://x.com/squashbionic/status/1759631239563386952?

CWF is 12 compute tiles, 3 base tiles and 2 I/O tiles. 17 in total. I/O tile reused from Granite Rapids

https://x.com/squashbionic/status/1760367618253627410?s=46&t=Go9LM3iS24APoFi_ulHkGw

 

[DavidC1]

CWF is 12 compute tiles, 3 base tiles and 2 I/O tiles. 17 in total. I/O tile reused from Granite Rapids

https://x.com/squashbionic/status/1760367618253627410?s=46&t=Go9LM3iS24APoFi_ulHkGw

32 cores per compute tile for a total of 384 with only 288 active.

 

[ashFTW]

32 cores per compute tile for a total of 384 with only 288 active.

Link?

 

[Markfw]

32 cores per compute tile for a total of 384 with only 288 active.

Those are E-cores, correct (essentially) If so, it does not stand a chance against Bergamo, let alone the Zen5 equivalent.

 

[adroc_thurston]

it does not stand a chance against Bergamo

Oh CWF kills it cleanly.

let alone the Zen5 equivalent.

That's a real tough fight.

 

[itsmydamnation]

Oh CWF kills it cleanly.

That's a real tough fight.

i know intel thread but......

take zen2 from x/y/z console process port , apply "Dense optimisation"
????????
profit ?

no that i expect AMD to do that.

funny in 2024 we are talking about flock of chickens like is a57 allover again.

 

[adroc_thurston]

take zen2 from x/y/z console process port , apply "Dense optimisation"
????????
profit ?

No, CSP wants around 256 vCPU per socket so spam is bad.

funny in 2024 we are talking about flock of chickens like is a57 allover again.

No we're like sub 300 vCPU per P or therein.
192-256.

 

[controlflow]

Those are E-cores, correct (essentially) If so, it does not stand a chance against Bergamo, let alone the Zen5 equivalent.

You realize those aren't Gracemont E cores and it is on 18A?

 

[adroc_thurston]

You realize those aren't Gracemont E cores and it is on 18A?

And this is Zen5c on N3e.
Now what?

 

[controlflow]

And this is Zen5c on N3e.
Now what?

No.
Bergamo is Zen 4c.

 

[adroc_thurston]

No.
Bergamo is Zen 4c.

CWF isn't competing with Bergamo.
It's a far more expensive part positioned against Turin-Dense.

 

[controlflow]

CWF isn't competing with Bergamo.
It's a far more expensive part positioned against Turin-Dense.

I didn't say it was. He was saying CWF doesn't stand a chance against Bergamo.
That is very unlikely to be the case.

 

[DavidC1]

Those are E-cores, correct (essentially) If so, it does not stand a chance against Bergamo, let alone the Zen5 equivalent.

Never talked about competition, but apparently you are threatened by any mention of a "superior" Intel part like it's your own child's business.

 

[igor_kavinski]

"superior"

Doesn't support AVX-512 and will be more expensive. AMD's competitive part will still sell out.

 

[Markfw]

Never talked about competition, but apparently you are threatened by any mention of a "superior" Intel part like it's your own child's business.

I am just sick of people defending E-cores against AMD C cores, there is a big difference. So, we will just see when they are available what the competition is and which is superior.

 

[dullard]

I am just sick of people defending E-cores

I am sorry that you are sick of it and yet I still will comment. But, I think there is a fundamental point that keeps getting missed. Intel E-cores (when compared to Intel P-cores) perform their best in low power per core situations. The E-cores perform terribly in higher power per core situations. What power level will each core in Clearwater Forest have? Roughly 1 W to 2 W each (give or take depending on model)? Now look at E-core vs P-core performance near that 1 W to 2 W power per core:

https://i0.wp.com/chipsandcheese.com/wp-content/uploads/2022/01/image-16-1.png?ssl=1

Yes, you are correct that E-cores have been over-defended and often over-hyped. But large core count situations is where E-cores really can shine. If AVX-512 is needed, the E-cores are the wrong way to go. But, otherwise I don't think you can compare what you think of high power per E-core performance to what will happen at low power per E-core. In other words, forget whatever you think you know about E-cores until these chips come out.

 

[mikk]

32 cores per compute tile for a total of 384 with only 288 active.

Physically only has 288 cores

https://twitter.com/x/status/1760987514754789413