Discussion Intel current and future Lakes & Rapids thread

[DrMrLordX]

~5-15% performance uplift

Wait, what? Even the leaked slide for 8+16 Arrow Lake (node not indicated) was saying +~20% vs. Raptor Lake @ 250W PL2. Unless I read it wrong?

 

[Henry swagger]

That isn’t what Intel says. Intel is using Intel 20a, which is a 2nm class node. I know that some here have indicated they are dual sourcing for compute chiplets, however they’ve all but denied this.

The power limit reduction is in line with Intel 20a. Notice that Intel (according to the earlier rumor) dropped their power limits just enough to be in line with AM5 parts.

Regardless of process, It is beginning to become clear what Arrow Lake is (I already suspected something like this was going on, glad to see I wasn’t wrong)

~5-15% performance uplift, 40%+ power reduction (huge perf/watt improvement)

Intel won’t get all the credit they deserve. They are fixing their perf/watt issues. Bravo. I look forward to further details.

20A is for mobile and client is N3

 

[igor_kavinski]

They could do Raptor Lake Refresh Refresh.

How dare they not have Nova Lake backported to Intel 7++++? <<< The question I would demand to know the answer to if I were an Intel investor.

How long must we endure their stale Alder Lake arch in desktop? <<< My question as an enthusiast.

When is Intel gonna put on their big boy pants and start making CPUs like they used to (Dothan/Nehalem/Haswell)? Alder Lake doesn't count coz it's using the e-cores cluster as a crutch.

 

[Geddagod]

That isn’t what Intel says.

Hmmm...

I know that some here have indicated they are dual sourcing for compute chiplets

Haven't seen a single leaker deny it. Not a single source. Not RGT, not MLID, not Adroc, not Exist50, literally not a soul.

however they’ve all but denied this.

That's just so much cap.

The power limit reduction is in line with Intel 20a. Notice that Intel (according to the earlier rumor) dropped their power limits just enough to be in line with AM5 parts.

Also in line with N3..

 

[Geddagod]

When is Intel gonna put on their big boy pants and start making CPUs like they used to (Dothan/Nehalem/Haswell)?

When are you going to put on your big boy pants and start contributing to any threads? I swear three fourths your comments are just meme-ing on Intel... even on AMD threads lmao

Alder Lake doesn't count coz it's using the e-cores cluster as a crutch.

Zen 2-5 doesn't count because AMD is using chiplets with trash packaging and high latency. What a crutch.
Don't get people's hate boners for E-cores smh.

 

[igor_kavinski]

When are you going to put on your big boy pants and start contributing to any threads?

Me no engineer.

Zen 2-5 doesn't count because AMD is using chiplets with trash packaging and high latency. What a crutch.

How do you know it's trash? Is AMD using something better for server/TR and if so, does the better packaging translate to real world performance gains?

 

[Geddagod]

https://x.com/9550pro/status/1710815028977528948?s=20

Mega chonk L3 cache, can't wait for latency results lol.
Hopefully SPR's poor bandwidth problems are improved.
One has to wonder how high L3 latency is going to get by the time we get into GNR and prob even DMR, considering how LNL looks to be changing it's cache structure for even larger core-private caches.

 

[AMDK11]

When is Intel gonna put on their big boy pants and start making CPUs like they used to (Dothan/Nehalem/Haswell)? Alder Lake doesn't count coz it's using the e-cores cluster as a crutch.

I would say Conroe, Nehalem and Haswell. As for Big/Small, it's already a chosen path for summer access and there's no quick application to move away from it.
Sunny/CypressCove and GoldenCove are back to strong core expansion and I predict LionCove will continue this trend.

 

[Hulk]

https://x.com/9550pro/status/1710815028977528948?s=20

And there's our Raptor Refresh review.
If those number are legit I think clocks are as follows.

14900K - 6GHz ST, 5.7GHz MT P, 4.4GHz MT E
14700K - 5.6GHz ST, 5.4GHz MT P, 4.1GHz MT E

Of course power is still a mystery but I bet it's still off the charts.

 

[Hulk]

I would say Conroe, Nehalem and Haswell.

It is my opinion that the Big/Little approach is more relevant today than simply making all cores the same.

Single thread and multithread compute are different animals.

Assume due to economic constraints you have a given die area to produce a part.
If you were to design the part to ONLY run MT applications, and perfectly scaling ones at that (think Cinebench) then you would cram as many E cores onto the chip as possible because they are more area efficient for MT than P cores. Let me back up that claim.

1 P at 6GHz would do about 3000 points CB R23 while an E core cluster at 4.3GHz would do about 4500 CB R23 points. Truth be told 1P is not as large as an E cluster, but the E cluster is not 50% larger as is indicated by the performance increase of the E cluster. It's more like 27% larger. Also MT P's at 6GHz is kind of unrealistic but the point is for pure MT performance die area is best filled with E cores for maximum performance.

Now if you strictly need ST performance you'd want 1 giant super fast P core. Or maybe 4 or 5 just to be sure you had enough of them. Maybe you'd even want 8 just to be "safe!"

So now if you want a part that is good at both ST and MT you'd want enough P's to handle your ST applications and then a bunch of E clusters to increase MT performance.

So why didn't AMD do it first? Probably because with their process advantage they didn't need to deal with the additional design and fabrication complications and cost. They were already in the lead performance-wise. Intel on the other hand didn't have the luxury of the TMSC nodes and needed to figure out a way to compete on a less advanced node and they did it. If AMD had gone to hybrid with Zen 4 they would have smashed Alder Lake and Raptor Lake.

The point is moving forward as more and more applications become increasingly multithreaded the hybrid approach will make more and more sense.

 

[igor_kavinski]

The point is moving forward as more and more applications become increasingly multithreaded the hybrid approach will make more and more sense.

The best thing would be compilers optimizing the application codepaths so that the most performance sensitive functions/threads are executed on the P-cores. The E-cores are fine for background tasks or anything that you just leave running and may check back in a few minutes or even hours coz it's not that urgent.

Cinebench 2024 Scores [CPU & GPU] (Updated Results)

The new Version of Cinebench, 2024, benchmarks CPUs and GPUs in the popular Redshift render engine. We benchmarked all modern CPUs and GPUs and list them in our score overview.

www.cgdirector.com

7950X is leading in MT score and that's at lower power consumption. Intel has a long way to go before they can exceed let alone match Zen's perf/watt.

 

[dullard]

The best thing would be compilers optimizing the application codepaths so that the most performance sensitive functions/threads are executed on the P-cores.

Why would the best thing be the complier doing it? The best thing is the programmer doing it. The programmer knows better than anyone if it is a time-critical thread or not.

 

[igor_kavinski]

Why would the best thing be the complier doing it? The best thing is the programmer doing it. The programmer knows better than anyone if it is a time-critical thread or not.

It would be less cumbersome if the compiler were to do it. It is feasible to design a compiler that understands how long certain instruction mixes will take to execute so put those on the P-cores. For the programmer to do that, a lot of experience is required and it won't solve anything because companies don't always hire the best and brightest.

Besides, the number of programmers that are able to analyze code performance and optimize it, makes up a really small percentage of the total programmer population of the world. It's hard enough to teach people to code. Optimizing code is a dark art and very few are able to get there. Better compilers are the solution.

 

[ondma]

The best thing would be compilers optimizing the application codepaths so that the most performance sensitive functions/threads are executed on the P-cores. The E-cores are fine for background tasks or anything that you just leave running and may check back in a few minutes or even hours coz it's not that urgent.

Cinebench 2024 Scores [CPU & GPU] (Updated Results)

The new Version of Cinebench, 2024, benchmarks CPUs and GPUs in the popular Redshift render engine. We benchmarked all modern CPUs and GPUs and list them in our score overview.

www.cgdirector.com

View attachment 86870

7950X is leading in MT score and that's at lower power consumption. Intel has a long way to go before they can exceed let alone match Zen's perf/watt.

"Leading" by 2.1% in multi while intel is "leading" by 4.8% in ST (comparing to 13900K, not KS). Come on man, performance is pretty much a wash.

 

[Hulk]

The best thing would be compilers optimizing the application codepaths so that the most performance sensitive functions/threads are executed on the P-cores. The E-cores are fine for background tasks or anything that you just leave running and may check back in a few minutes or even hours coz it's not that urgent.

Cinebench 2024 Scores [CPU & GPU] (Updated Results)

The new Version of Cinebench, 2024, benchmarks CPUs and GPUs in the popular Redshift render engine. We benchmarked all modern CPUs and GPUs and list them in our score overview.

www.cgdirector.com

View attachment 86870

7950X is leading in MT score and that's at lower power consumption. Intel has a long way to go before they can exceed let alone match Zen's perf/watt.

Yes you are right. But I don't know why you quoted me? As I wrote above AMD has a process advantage over Intel. Their lead would even be larger in MT if they used a hybrid approach. AMD has that card in their back pocket when they need to pull it.

 

[dullard]

It would be less cumbersome if the compiler were to do it. It is feasible to design a compiler that understands how long certain instruction mixes will take to execute so put those on the P-cores. For the programmer to do that, a lot of experience is required and it won't solve anything because companies don't always hire the best and brightest.

Besides, the number of programmers that are able to analyze code performance and optimize it, makes up a really small percentage of the total programmer population of the world. It's hard enough to teach people to code. Optimizing code is a dark art and very few are able to get there. Better compilers are the solution.

Compilers can potentially tell what takes a long time to execute and what can be executed quickly. But, they probably do not know importance of the tasks without programmer knowledge. Easiest example that I can think of is a background virus scan of the whole computer. That might take hours to do. Should the compiler thus put it as a priority on a P core? Or course not. That background scan should run on an E core. ANY programmer would know that.

Example 2: gaming. The explosion animation thread is of an utterly low priority, but it is quite computationally expensive for both the CPU and somewhat for the GPU. Does it matter if some of the explosion animation is delayed 1 frame? Of course not. Even though it is computationally expensive, it is not important to be timely (certainly not within 10s of milliseconds). That animation calculation belongs on an E core (plus GPU). The actual time-critical gameplay should be on the P cores to avoid lags or stutters. A compiler would not inherently know that the computationally expensive explosion math is unimportant.

You have a point about optimization, but this isn't an optimization task. It is a prioritization task. Much easier for just about any programmer.

 

[igor_kavinski]

Come on man, performance is pretty much a wash.

At the cost of much higher power draw in all core workloads.

 

[igor_kavinski]

Yes you are right. But I don't know why you quoted me?

I agree with your hybrid approach thoughts. However, until and unless AMD jumps in with their implementation, we won't know how good it can really be. Intel is just working in a panicky damage control mode. Their main objective is not to lose face in the public eye. They could also change their tactics abruptly if they manage to come out with a highly performant and small core and then ditch hybrid or put 4 E-cores in the SoC tile and call it a day.

I think it is very telling that instead of asking Microsoft to put in a right click context menu option or a developer hint in the executable to run only on P-cores, they outright disabled AVX-512. They are currently in full bone-headed moronic mode and it will probably only stop if AMD messes up big time and let's Intel breathe a sigh of relief.

 

[nicalandia]

60 Core Emerald rapids taking 4th place in Sisoftware Aritmethic ranking, right above 56 Core SPR but below 48 Core Genoa all system were 2S

Top Processor Arithmetic Ranks

ranker.sisoftware.co.uk

 

[Henry swagger]

Official Intel Slides Show Core i9-14900K CPU Up To 23% Faster Than AMD Ryzen 9 7950X3D In Gaming

A leaked Intel slide has compared the gaming performance of the flagship Core i9-14900K with the AMD Ryzen 9 7950X3D CPU.

wccftech.com

Can't wait for reviews with the new ram

 

[eek2121]

Hmmm...
View attachment 86864

Haven't seen a single leaker deny it. Not a single source. Not RGT, not MLID, not Adroc, not Exist50, literally not a soul.

That's just so much cap.

Also in line with N3..

Uh, you do understand that even on Meteor Lake, TSMC is used for graphics, etc, right? Meteor Lake is not dual sourced, yet it is listed right there next to arrow lake. This slide (and variants of it) keep getting brought up, but I strongly suspect you folks are taking it out of context.

However, I am done having this argument. I have said my piece. We will see how things play out.

 

[Geddagod]

Uh, you do understand that even on Meteor Lake, TSMC is used for graphics, etc, right? Meteor Lake is not dual sourced, yet it is listed right there next to arrow lake. This slide (and variants of it) keep getting brought up, but I strongly suspect you folks are taking it out of context.

However, I am done having this argument. I have said my piece. We will see how things play out.

MTL is listed right under Intel 4. ARL is listed under "external N3" and "Intel 20A". Notice how the block specifically says "external N3" not just "External". We know MTL uses no N3 tiles, so hence it has to be for ARL. And we know they are only talking about compute tiles, else they would list "external N5" for the GPU tile in MTL.

 

[Geddagod]

You know, looking at all the recent talk about Intel's next couple CPU generations, one has to wonder how Intel is supposed to compete with Zen 6 in 2025 with PTL and ARL-R, both which appear to be esentially LNC based. MT I'm guessing is not really a problem (since Intel looks like they can just spam the cinememe cores lol) but based on AMD's historical cadence, would Zen 6 not be esentially a full to half generation ahead in single core performance?

 

[H433x0n]

You know, looking at all the recent talk about Intel's next couple CPU generations, one has to wonder how Intel is supposed to compete with Zen 6 in 2025 with PTL and ARL-R, both which appear to be esentially LNC based. MT I'm guessing is not really a problem (since Intel looks like they can just spam the cinememe cores lol) but based on AMD's historical cadence, would Zen 6 not be esentially a full to half generation ahead in single core performance?

Perhaps ARL-R will fix a lot with 300-400mhz higher clocks. I also don’t think Zen 5 is going to bring some crazy 1T perf increase.

 

[Geddagod]

Perhaps ARL-R will fix a lot with 300-400mhz higher clocks. I also don’t think Zen 5 is going to bring some crazy 1T perf increase.

Even a ~20% increase in ST perf, which shouldn't be crazy at all, would bring parity between Zen 5 and ARL. I struggle to see how a small percentage increase in clocks could help overcome the likely 10-20% increase in ST performance Zen 6 is likely going to bring. Not to mention the
-X3D skus in gaming.