Lets wait for tests before you talk.. and watch your tone mr mydamn lol
no lets physics...... your statement makes zero sense based on known behaviour of semiconductors at the sizes we are talking about . Furthermore this isn't even a new behaviour its been a dominating factor since 14nm if not before. 80mm sq , 200mm sq , 500mm sq it matters not.
let not forget that in general intel doesn't always use the best thermal product between the die and the head spreader. So unless the move to solder across the board that's an actual disadvantage.......
i went looking cuz i know he will come back with trash but i found this very good paper:
look at figure 19, an i7-8650U..... look how usefull all that non core die area is for heat dissipation and that only a 14nm processor , it only gets worse in term of heat density from there....
look at figure 19, an i7-8650U..... look how usefull all that non core die area is for heat dissipation and that only a 14nm processor , it only gets worse in term of heat density from there....
Were you sleeping guys?
Arrow Lake is using 20A for the CPU tile and TSMC N3 for the GPU tile.
They’re not, this is just TSMC silicon. There’s no scaling with power - it just turns into a hair dryer that’s impossible to cool.
It's dual sourced, N3(most likely B) is used for the CPU tile as well. It's understandable Intel doesn't want to confirm it though, considering how it would effect stock lol.
NVIDIA下代B100訂單簽定 台積電7/5/3奈米大客戶全回歸
下半年確實寒冬未過，但對台積電來說卻沒那麼冷，受惠來自中國AI晶片客戶急單挹注，及NVIDIA、英特爾（Intel）、超微（AMD）與眾多美系大廠訂單回溫，10月起先前崩跌的各製程產能利用率將逐月回升，加上蘋果（Apple）新單放量與強勢美元成為大補丸，業績...
www.digitimes.com.tw
Taiwanese media says that the demand of Intel for N3 is not established yet.
Probably, Intel prioritize their own node, Intel 20A and simply think of N3 as an insurance.
Based on Adored TV slides, it appears as if the TSMC N3 plan was the original plan, with whatever Intel node they could use as some extra help.
ARL prob started design sometime in 2018-2019, and at that time Intel's node issues were still in full swing.
DrMrLordX
Lifer
- Apr 27, 2000
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Intel might have bagged on N3 for Arrow Lake entirely if their initial plan was to port Arrow Lake to 20a and N3B. N3E has different design rules, meaning that Intel possibly would have needed to port Arrow Lake to three different nodes thanks to their decision to delay taking wafers (so as to avoid N3B entirely).
The above assumes, of course, that Intel's decision to delay taking N3-family wafers is an attempt to avoid N3B.
However, I shudder to think what happens to them if they're forced to rely on 20a for both 6+8 and 8+16 tiles.
The above assumes, of course, that Intel's decision to delay taking N3-family wafers is an attempt to avoid N3B.
However, I shudder to think what happens to them if they're forced to rely on 20a for both 6+8 and 8+16 tiles.
NVIDIA下代B100訂單簽定 台積電7/5/3奈米大客戶全回歸
下半年確實寒冬未過，但對台積電來說卻沒那麼冷，受惠來自中國AI晶片客戶急單挹注，及NVIDIA、英特爾（Intel）、超微（AMD）與眾多美系大廠訂單回溫，10月起先前崩跌的各製程產能利用率將逐月回升，加上蘋果（Apple）新單放量與強勢美元成為大補丸，業績...www.digitimes.com.tw
Taiwanese media says that the demand of Intel for N3 is not established yet.
Probably, Intel prioritize their own node, Intel 20A and simply think of N3 as an insurance.
A few select quotes below (translated to English):
Not sure how these quotes are supposed to be interpreted due to the language barrier. What do they mean by “meet”? I wouldn’t say this article suggests that Intel might bail on N3B.
If they rely solely on 20A it wouldn’t be bad news. It’d mean that they had the yield / performance to do it. If 20A doesn’t appear to be ready they would just stick with plan A. It’d be a bullish sign overall.
It means if Intel proceeds with projected/contracted Arrow Lake allocation, then TSMC will benefit from it cause TSMC has basically excluded Intel's N3B orders for the moment. So the decision is on Intel's hand, of course Intel will try to use IFS for all ARL's tCPU; it depends on yields especially for 8+16 tile
They (Intel) have a much higher TDP limit, so by definition you're just incorrect. Perhaps you're mistaking AMD's chips running hotter for being more difficult to cool. It really doesn't matter what temperature the core is at, what matters is how much heat the cooling system needs to dissipate and AMD has lower caps on how much power their CPUs can consume and therefor how much heat they generate.
Intel's chips aren't any more difficult to cool if not using those higher power limits, but because you theoretically could, you need an high-end air cooler or better yet a water block if you want to push 200+ Watts to it. Unless you're trying to overclock an AMD CPU it'll probably run fine with the included box cooler for the models that come with one. Even though Zen 4 had a higher power limit than previously, the chips really don't benefit from it and are much better running below 100W and closer to the same power levels as with Zen 3.
Intel is not only able to use I20A but also I3.
Frankly, N3B is alike Intel 10nm+, Ice Lake, which is the process as useless as trash.
(N3A is alike Intel 10nm, Cannon Lake... It was a catastrophe!!)
I don't think that Intel is going to rely on this.
Intel might use N3E or N3P.
Anyway, the most worthy process for Intel is their own node.
TSMC's wafers are simply supplements.
IDM 2.0 strategy opened Intel's process choices, however, didn't reverse their priority order.
There’s thermal density and thermal transfer that needs to be considered.
A good example is the 13700H vs 7840HS comparison video I posted a few pages back. The 13700H was able to push more power than the 7840HS before thermal throttling despite them both being in the same chassis and using the same cooler.
There’s also SPR workstation chips that push considerably more power than a 13900K and yet are considerably easier to cool due to the better thermal transfer from the much larger IHS.
Using the same components from my old 7950X system (sans CPU & motherboard) I’m able to keep my 13900K below 90* C at 253W. Whereas with the 7950X I wasn’t able to keep it below 90* C once it passed 160-170W.
All links must be accompanied by your own commentary.
DrMrLordX
Lifer
- Apr 27, 2000
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That's making a lot of assumptions. N3B is already having yield problems, at least by TSMC standards, which is why Intel appears to be skipping it entirely (or is at least trying to). So to reiterate, they already have Arrow Lake laid out on 20a (6+8) and N3B (8+16). Skipping N3B entirely means one or more of the following:
1). No 8+16 chiplets, at all. Seems unlikely, especially after the Meteor Lake, er, ahem "situation"
2). Spend lots of time and money porting Arrow Lake to N3E and hope it gets close to the current launch window. That's risky. If TSMC doesn't hit their production targets perfectly for N3E or if it's going to take too long for Intel to port Arrow Lake over to N3E (or if it's just too expensive for the suits upstairs) then you get
3). Intel sucks it up and decides to use 20a for everything, including all the fun yield goblins on larger die sizes that caused them to source extra N3B capacity from TSMC for Arrow Lake chiplets in the first place
They simply can't use N3B for Arrow Lake compute chiplets now since, apparently, Intel has delayed wafer delivery and now Apple has all TSMC's remaining N3B capacity. Even if 20a proves to be a bloody disaster for 8+16 chiplets (which, again, is allegedly why Intel was avoiding that in the first place), they simply may not have another option.
On top of all that, we still don't know if Intel is volume constrained by EUV equipment availability.
@lightisgood
N3A? Do you mean N3AE? That's meant for automotive, and uses the same PDK as N3E (apparently). I've seen no reports of good or bad things about that node, and unless you're working for Bosch or Denso or someone like that, you'll probably never know.
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Arrow power limits revealed.. tsmc N3 lookinh good 43% more efficient at pl2 than intel 7 node 😃💻
Alleged Intel Arrow Lake-S CPU Power Limits Revealed: 125W PL1, 177W PL2, 333W PL4 For 8+16 Core Unlocked SKU
Alleged power limits of Intel's Arrow Lake-S Desktop CPU featuring 8 P-Cores and 16 E-Cores have been revealed by Darkmont.wccftech.com
That isn’t what Intel says. Intel is using Intel 20a, which is a 2nm class node. I know that some here have indicated they are dual sourcing for compute chiplets, however they’ve all but denied this.
The power limit reduction is in line with Intel 20a. Notice that Intel (according to the earlier rumor) dropped their power limits just enough to be in line with AM5 parts.
Regardless of process, It is beginning to become clear what Arrow Lake is (I already suspected something like this was going on, glad to see I wasn’t wrong)
~5-15% performance uplift, 40%+ power reduction (huge perf/watt improvement)
Intel won’t get all the credit they deserve. They are fixing their perf/watt issues. Bravo. I look forward to further details.
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