But to get those 17% you ll have to increase wattage by 40-45% or so, and even at stock perf/watt is at a disadvantage in respect of the 9554 due to Epyc s node advantage...
But to get those 17% you ll have to increase wattage by 40-45% or so, and even at stock perf/watt is at a disadvantage in respect of the 9554 due to Epyc s node advantage...
While literally less than a week ago I was arguing with someone on Reddit that ST perf isn't all that important in server products, I wouldn't say it's worth nothing. Higher 1T was the quoted reason that Jensen said they went and paired SPR with their H100 systems- and even if that was just a "fake" reason so that they would have an excuse not to use AMD, there's plenty of benches in websites such as Phoronix that care mostly about ST performance- and that whole website is dedicated to testing workloads that are representative of common server use cases.
AMD even recognize this market as, even if niche, somewhat of an official market- which is why they sell server skus that are frequency optimized (AMD with their -F skus).
Intel's self quoted perf improvement with EMR was 17% improved perf/watt btw
No, it's 17% more general compute performance at iso power (350W). I'm not claiming it's amazing but it's unambiguously more performant than SPR.
There's a difference between 1T performance and per core performance. No one cares about 1T performance on server CPUs, but many customers do care about how each core performs once the CPU is loaded.
I finally understand the "ummm akshually" meme now lol
Everybody always has an issue when I link the Phoronix test results. Going by their results, SPR is within 25% of Genoa in their geometric mean of all results and outperforms Milan. I genuinely don't know how to interpret their findings though.
The geometric mean isn't all that useful. They mix in a bunch of ST, MT, and then AI based workloads (where Intel obviously dominates bcuz of accelerators) and call it a day. Using the individual breakdown of "sections" averages are much more useful.
In that case then they're beating Milan in every metric? All of these results are exact opposite of what I've heard online where Milan beats SPR and Genoa nearly doubles SPR performance.
It may seem that I’m trolling but I’m not. If those are legitimate / representative benchmarks then the tech enthusiast internet is a crazy place.
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dullard
Elite Member
- May 21, 2001
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The mathematically correct way to compare multiple benchmarks is a geometric mean, not just a simple average. That said, you are correct that a geometric mean of a mixture of irrelevant tests is not useful. If you care about MT, then do a geometric mean of just the MT tests. If you care about AI, then do a geometric mean of just the AI tests.
No, only on AVX-512 And specific accelerators, otherwise Milan will outperform SPR.
Epyc Milan vs Sapphire Rapids at ISO Core OpenBenchmarking Results
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… AVX512 and accelerators are part of SPR though? If AVX512 and AMX provide a big enough uplift allowing it to take the win in Phoronix’s test suite for HPC, Rendering, Code Compilation, etc that’s an accurate representation of what a buyer would receive if they ordered SPR.
But AVX512/AMX is not making any difference in many of those test(HPC, Rendering and Code Compilation) because the developers have yet to implement it, heck even AVX-512 has hardly been implemented.
Those are at ISO core count so Apples to Apples, perhaps With EMR they will be able to beat Milan?
According to Phoronix they’re beating Milan. When you’re comparing the entire processor and not just cherry picking a slice of 8 cores rented out.
Markfw
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- May 16, 2002
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But what happens when it is pitted against its competition, which is not Milan ?
Don't. You will get a few people upset here. We all know how weak SPR looks against Genoa.
It loses.
I’m not exactly an SPR cheerleader, I’m not advocating anybody to buy it.
I honestly don’t care. I find a lot of the data center stuff boring and it’s not exactly competitive at the moment between Intel and AMD.
Well Data Center is where they are "More" Competitive due to AVX/AMX because it gets worst at the desktop where their niche accelerators don't help https://www.pugetsystems.com/labs/articles/intel-xeon-w-3400-content-creation-review/
at stock it can't even beat Milan and it's barely ahead of Rome based ThreadRippers.
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To me, that’s essentially a Data Center comparison. Not exactly unexpected results either. To reiterate - I’m not white knighting for SPR.
I was just making a comment that the online discourse about this is wildly overstating the reality of the situation.
And that's the problem for Intel currently, such a slice on AMD is cherry picked, but pretty much impossible to make it perform on Intel.
1) Without on-socket NUMA, such tenant of 8C size does not have enough on core resources and any memory traffic is basically a L3 cache miss and looong trip to memory.
2) With quadrant mode, such tenant of 8C is awkwardly sized for 14C slice and has even more miniscule L3, mem bandwidth cut to 2 channel. Not a right place to be and memory subsystem performance is still hilariously bad for 2023.
Compare to AMD where such tenant is has full chiplet just for themselves, backed by their excellent L3 slice of 32MB and 96MB with X3D. And all L3 misses share same IOD with 12 channels.
EMR is fixing most of it by providing larger slice, way more L3 for "half" mode. So fortunes of Intel from performance side core vs core will improve quite some.
They won't be able to touch AMD's perf peaks obviously, but there are so called "licenzing bastards", where software vendor shenanigans are forcing orgs to buy certain sized servers anyway -> like 32C. Intel will be much more competitive in those if the price is right.
Intel Meteor Lake & Arrow Lake CPUs Might Feature Similar AI-Dedicated VPU Capabilities
Intel's Meteor Lake and Arrow Lake might feature a similar VPU for AI capabilities, suggesting that Intel plans for early-stage adoption.
wccftech.com
TSMC Moving Towards "Aggressive" Expansion of CoWoS Packaging Facilities For AMD & NVIDIA AI Chips
TSMC has bumped up orders for advanced CoWoS packaging equipment amid the influx of huge AI demand from tech companies such as NVIDIA & AMD.
wccftech.com
Gaudi3 isn't going to use CoWoS but EMIB ?
I'm surprised at EMIB performance because Gaudi3 must equip itself with HBM3e.
Attachments
Yes. 2S = 2P so two socket. 2S SF 288c/288T vs 2S Bergamo 256c/512T.Doesn't this slide say up to 288 cores on the 2S?
Few here got too carried away br OMG 288 Core Sierra Forest. Well its like the previous leaks. Only 144 per socket and... get this: 36 Quad Clusters each with 3 MiB of L3. Same internal ring per cluster. Good luck with that.
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That's SP (2 socket times 144). Then there is AP. This was the Hot Chips presentation. Then the CEO showed off AP which is clearly a different package that had two die together. That makes 288 within a package.
It's really pretty straight forward.
So if AP supports 2 socket...
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