Discussion Intel current and future Lakes & Rapids thread

[A///]

Always fun to see people play "My stepping is better than yours"

we're a few steps away from gunslinger losing his mind and thinking he's moses and parts the red sea but in this case his internal gusto claws at amd's datacenter figures and allows intel to recapture the sales channel.

 

[H433x0n]

we're a few steps away from gunslinger losing his mind and thinking he's moses and parts the red sea but in this case his internal gusto claws at amd's datacenter figures and allows intel to recapture the sales channel.

Well… somehow Intel’s datacenter did better than AMD’s QoQ.

 

[A///]

Ok so that's not awful for Intel but not fantastic. More impressive from AMD I think given that was Ice Lake to Tiger Lake (very minimal CPU IP change in particular though graphics sure), whereas the former was Renoir to Cezanne (major CPU IP change) and both were on a similar process.

tigerlake helped intel at the time with laptop sales. client sales weren't so well. client was rocket lake, a menace of a turd that was also a regression. it having avx512 is the only redeeming quality of rocketlake. it's no wonder intel fawned over the damn tiger lake stuff which prompted criticism by the professional tech press, and meme crap from the youtube riff raff.

 

[A///]

Well… somehow Intel’s datacenter did better than AMD’s QoQ.

last q call lisa said they had to adjust orders from tsmc. intel is still on the hook for delivering products via contracts. why did amd ship less? it could be cost or it could be businesses not needing as many intel servers when fewer epycs are going more work, cost less, and use less energy. too much of a good thing

 

[lightisgood]

last q call lisa said they had to adjust orders from tsmc. intel is still on the hook for delivering products via contracts. why did amd ship less? it could be cost or it could be businesses not needing as many intel servers when fewer epycs are going more work, cost less, and use less energy. too much of a good thing

Ugly.

Do you know ”Occam's razor” ?
Clearly, AMX meets AI market demand.

 

[Hitman928]

Well… somehow Intel’s datacenter did better than AMD’s QoQ.

Intel reported their worst quarter in over 20 years last quarter. Bouncing back from that, while a good thing, isn’t that impressive. Especially when their DC unit still isn’t making any money, despite the increased revenue.

 

[Exist50]

A couple weeks may be an exaggeration, but Intel was not limited by the speed of TSMC's hot lots. They could have much "hotter" lots than TSMC since they didn't have any other customers to worry about. That's the whole reason they adopted a more 'try it and see' approach than those who relied more on simulation to verify their designs because they used foundries that had other companies and were limited in how fast a single customer's hot lot could pushed through the fab in front of other customers.

It takes about a quarter no matter what (for a modern leading edge process). I'm only familiar with TSMC's timeline, but it's clearly asymptotic around 4-5 months, no matter how many millions extra you're willing to pay. Even if Intel was able to shave off a week for their internal teams, the math just doesn't work out.

 

[Exist50]

That's not necessarily true, I think it'd be extraordinarily difficult to get any modern CPU to be in shippable state while still on A-stepping silicon. AMD is still very efficient managing to ship on B-stepping which is very difficult to do on a CPU.

Intel:
13900K - B0 stepping
12900K - C0 stepping (Intel's first mainstream heterogeneous CPU)
11900K - B0 stepping

AMD:
7950X - B2 stepping
5950X - B0 stepping
3950X - B0 stepping

Nvidia - ruled by Jensen's iron fist and they always ship on A-stepping (also it's easier to ship a GPU on A-stepping compared to a CPU)
RTX 4090 - A1 stepping
RTX 3090 - A1 stepping
RTX 2080 Ti - A1 stepping
GTX 1080 Ti - A1 stepping

AMD may not always ship their lead Zen product on A-step silicon, but they've done it for the follow-ons like their mobile chips. That's a tradeoff they make. By serializing the APUs behind the desktop IP implementations (CPU and graphics), they're able to minimize the risk of bugs an engineering effort needed. The sacrifice is time to market. Still, even when they need a B-step, it's more about bug fixes and extra speed than it is getting a baseline bootable product. Even Intel can do that on A-step.

Intel, by contrast, seems to do everything in parallel, even the similar client dies (e.g. 8+8 vs 6+0 ADL-S). Combine this with poor quality tape outs, and you get far, far more steppings in total. They've just been able to hide that cost until now.

And even if you want to ignore AMD, Apple consistently does A-step PRQs, and with the first IP implementations too. It's all a matter of how much time and effort you're willing to spend on pre-silicon validation.

 

[Exist50]

5800h shipped A0. The 1165g7 shipped B1.

Just for the record, don't rely on the brand string for an accurate metal stepping number. You'll sometimes see "silent" steppings that the company doesn't want visible at a product level. And there will probably be more shenanigans with chiplets in the mix.

 

[igor_kavinski]

You'll sometimes see "silent" steppings that the company doesn't want visible at a product level.

So the chip needs to be inspected physically (stepping written on the heatspreader)?

Any example that comes to mind and why Intel wanted to keep it silent?

 

[A///]

Ugly.

Do you know ”Occam's razor” ?
Clearly, AMX meets AI market demand.

I don't see AMD moving instincts in large numbers compared to nvidia. if you mean the avx512 on epyc, nvidia's solution is still better. It is faster. If video cards, Nvidia is better supported. there is no one fighting tooth and nail to get their hands on instincts. amd and intel can dump software support and equivelance in feature set as Nvidia and they'd still suffer because people will always gravitate towards the proven platform. llm training is not cheap. no one has infinity budgets to sit around seeing what amd or intel are doing.

 

[A///]

It takes about a quarter no matter what (for a modern leading edge process). I'm only familiar with TSMC's timeline, but it's clearly asymptotic around 4-5 months, no matter how many millions extra you're willing to pay. Even if Intel was able to shave off a week for their internal teams, the math just doesn't work out.

Yep that's accurate. You might go upver but that's rare. no idea what intel can do themselves but it wouldn't stray far from that number mate.

 

[A///]

Any example that comes to mind and why Intel wanted to keep it silent?

neither amd nor intel cared much about steppings in the past until enthusiast circles began caring about them. then it became a big deal. A0 to A6 may signifiy a small amount of tiny changes or larger changes but not ones large enough to warrant dropping a B0 stepping. It's mostly wankery and people being obsessed with letters and numbers as if it's a bad or good thing. As a consumer it means either something was refined or fixed. I couldn't give a damn myself.

 

[Exist50]

So the chip needs to be inspected physically (stepping written on the heatspreader)?

Any example that comes to mind and why Intel wanted to keep it silent?

I'm not aware of any way to tell if they don't include it in either the brandstring or the label, nor do I know why it's a thing. Never seen an example myself to learn why.

 

[SiliconFly]

Well… somehow Intel’s datacenter did better than AMD’s QoQ.

I was under the impression Intel's server market share is in a steady decline. Even now.

 

[A///]

I was under the impression Intel's server market share is in a steady decline. Even now.

intel still holds contracts they must fill out for or they can terminate and pay a heavy fee for. this is what gets their less than ideal xeons still sold in a market where epyc is the better choice all around. once those contracts run out intel is either left holding a stack of useless processors or comes out with something that rivals epyc in performance and energy use. hyperscalers, dcs and other companies who aren't under contract will buy a mix of intel and amd or amd only, or if their stack and testing time doesn't permit it, they go with the safer choice of intel since they've qualified their hardware enough to know it's general safe for us. I expect the last of those contracts to expire some time in 2027-28

 

[Exist50]

intel still holds contracts they must fill out for or they can terminate and pay a heavy fee for. this is what gets their less than ideal xeons still sold in a market where epyc is the better choice all around. once those contracts run out intel is either left holding a stack of useless processors or comes out with something that rivals epyc in performance and energy use. hyperscalers, dcs and other companies who aren't under contract will buy a mix of intel and amd or amd only, or if their stack and testing time doesn't permit it, they go with the safer choice of intel since they've qualified their hardware enough to know it's general safe for us. I expect the last of those contracts to expire some time in 2027-28

Any SPR contracts Intel might have had were surely lost with the delays and other issues. I don't see this being a realistic reason in 2023.

 

[Khato]

I was under the impression Intel's server market share is in a steady decline. Even now.

Intel's market share of profitable data center sales is almost certainly in decline as AMD simply has a better product for the high end. But the combination of accelerators and price are apparently adequate to keep the revenue marketshare from further decline. Keep in mind that selling a Xeon for a minor loss can still be better than idle fab equipment.

 

[Thunder 57]

Intel's market share of profitable data center sales is almost certainly in decline as AMD simply has a better product for the high end. But the combination of accelerators and price are apparently adequate to keep the revenue marketshare from further decline. Keep in mind that selling a Xeon for a minor loss can still be better than idle fab equipment.

I never really understood that argument. It sounds an awful lot like the joke "We sell at a loss, but make it up with volume.".

 

[eek2121]

At least AL and RL are competitive at some point. From the leaks so far, it appears ARL will not be competitive at higher power, so how does it follow that it will be somehow magically be competitive or better at lower power? (Yes, I know it is theoretically possible, depending on the characteristics of the node, but until I actually see it in hard data, that just seems like wishful thinking.)

That chart was taken out of context, but to answer your question: For the same reason you can drop the power limit 35% or more on a 7950X and lose very little performance. Once these chips reach a certain point, it takes a tremendous amount of power to move the performance needle even a tiny bit.

 

[ondma]

That chart was taken out of context, but to answer your question: For the same reason you can drop the power limit 35% or more on a 7950X and lose very little performance. Once these chips reach a certain point, it takes a tremendous amount of power to move the performance needle even a tiny bit.

I understand that, but I would think if the performance was relatively a lot better at lower power, they would have used that number instead.

 

[Khato]

I never really understood that argument. It sounds an awful lot like the joke "We sell at a loss, but make it up with volume.".

It does indeed sound like such, but in this case it's just a matter of it being better to have a $1 loss by manufacturing and selling the chip rather than a $2 loss from having fab equipment idle. (The dollar figures are, of course, fictional representations.) It's obviously not a sustainable operating model, but the current fabs and equipment are already bought and paid for. It's best to make as much money from that investment as possible rather than just let it depreciate away to nothing.

Intel's current spending spree on new fabs/equipment clearly indicates that they don't expect to remain uncompetitive.

 

[Geddagod]

I understand that, but I would think if the performance was relatively a lot better at lower power, they would have used that number instead.

These are internal (well counting OEMs as well lol) projections, there was no need to sugar coat anything to the public. Even if it stops scaling way earlier in the power curve, both Intel and AMD have been pushing MT clocks to the max for no reason other than kicks and giggles (and trying to one up each other in benches).
PL2 is likely to remain high as well, since even if it's not for this specific generation, it's possible future chips (cough 8+32) would be able to much better utilize the extra power.

 

[A///]

Any SPR contracts Intel might have had were surely lost with the delays and other issues. I don't see this being a realistic reason in 2023.

this would come up. if Intel fails or renegs that's one thing, but the buyer will also pay a penalty or kill fee for the contracts outstanding. Intel would pay for leaving their customers in a lurch, but someone would have to pay for intel's wasted and I say this trying to stifle a laugh r n d efforts. contracts like this will include a termination or kill fee or penalties for being late. in your example intel may have handed over those processors for free as penalty. this tracks given their lateness and poor income.

 

[Khato]

PL2 is likely to remain high as well, since even if it's not for this specific generation, it's possible future chips (cough 8+32) would be able to much better utilize the extra power.

Indeed. So many are incorrectly assuming that the PL1=PL2=250W means that's how much power the ARL SKU in question needs to achieve the specified performance. This is similar to the i7-13700k and i9-13900k both having a 253W max turbo power, but the i7 part both doesn't reach that max power consumption and offers notably lower performance. The 8+32 ARL part will have markedly higher MT performance with the same power budget, while the same 8+16 with non-k power levels (maybe still same 65W PL1, 219W PL2 as raptor lake) will be the true mark of how much efficiency has improved. Unfortunately those weren't the numbers that were leaked.