Discussion Intel current and future Lakes & Rapids thread

[Exist50]

Pretty sure they always start at A. You just don't always hear about an 'A' because if it completely fails to function at all it is superceded in a couple weeks by B and so on.

They always have something that starts with A, but seem to name the derivatives differently. Like the TGL 8c started at P or something. Likewise for the ADL 6+0 die.

And you definitely can't pull off a full layer stepping in a couple of weeks. Even if you taped out instantly (which is impossible, as it takes weeks to get the design finalized, masks made, etc.), it takes about a full quarter to get first silicon out of the fab. And that assumes you're paying a fortune for TSMC ultra-mega-super-hot lots (name barely an exaggeration).

 

[Abwx]

AFAIK, Intel 7 equips novel metal stacks, UHP library and demands novel EDA tools.

As said 10nm SF has been renamed Intel 7 and is already in use in RPL, that was stated in a slide from Intel, otherwise RPL-S wouldnt have only 2-3% better perfs.

Intel Raptor Lake-S: Mehr Kerne, Takt und TDP für (viel) mehr CPU-Leistung

Ein „signifikant verbesserter Fertigungsprozess“ soll Raptor Lake von Intel Beine machen und gegen AMD Ryzen 7000 bestehen lassen.

www.computerbase.de

 

[coercitiv]

It’s the alleged concern over efficiency that falls apart once it’s paired with a GPU that will consume more power at idle (with multi-monitor high refresh) than their CPU could consume at full tilt. In less demanding games, the 4080 will consume 100W+ less power.

What makes you think that people who boast about their efficient CPU have multi-monitor high refresh setups? A fast multi-monitor setup defeats the idea of energy efficiency no matter the choice of your GPU. Also, if you enable VRR, the 7900XT has good idle power consumption.

Spoiler: VRR vs. Fixed refresh

The 7900XTX clearly has some power consumption issues with light games, especially when compared with RDNA2 cards that have excellent scaling with light gaming. That being said, you're trying very hard to make a point about AMD GPUs in an Intel CPU thread.

Edit: Thinking about this more, the internet hates Nvidia’s Ada Lovelace cards for the same reason they favor Ryzen. The Ada Lovelace line is class leading with its incredible area and power efficiency. They also are very good at re-using their gaming / enthusiast dies for revenue in workstation / data center. Nvidia’s big margins and silicon efficiency makes their cards hated and considered a bad value / rip-off to enthusiasts. Yet these same principles makes Ryzen great and consumers are happy to contribute to AMD’s big margins.

I think you need to think about this even more: AMD is currently getting the same treatment for RDNA3 that Nvidia is getting for Ada. You should visit the GPU forum more often and discover how Ada's efficiency is just about the only universally appreciated feature of the new generation, while the very poor performance per dollar and VRAM starving of the "value" cards are the real reasons Nvidia is getting burned. Ada Lovelace is not just the 4090 and the 4080.

 

[mikk]

As said 10nm SF has been renamed Intel 7 and is already in use in RPL, that was stated in a slide from Intel, otherwise RPL-S wouldnt have only 2-3% better perfs.

They renamed 10ESF not 10SF.

 

[lightisgood]

Intel Lunar Lake CPUs Feature 64 Xe “Battlemage” EUs For iGPU, 8 Xe-Cores & Next-Gen VPU

Intel Lunar Lake CPUs Feature 64 Xe "Battlemage" EUs For iGPU, 8 Xe-Cores & Next-Gen VPU

Intel next-generation Lunar Lake "Core Ultra" CPUs for low-power PCs will feature up to 64 EUs based on the Battlemage Xe2-LPG iGPU cores.

wccftech.com

 

[mikk]

Intel Lunar Lake CPUs Feature 64 Xe “Battlemage” EUs For iGPU, 8 Xe-Cores & Next-Gen VPU

Intel Lunar Lake CPUs Feature 64 Xe "Battlemage" EUs For iGPU, 8 Xe-Cores & Next-Gen VPU

Intel next-generation Lunar Lake "Core Ultra" CPUs for low-power PCs will feature up to 64 EUs based on the Battlemage Xe2-LPG iGPU cores.

wccftech.com

Maybe they should have mentioned that Battlemage EUs are beefed up to SIMD-16 up from SIMD-8 Alchemist/MTL and at the same time there is no dual subslice. Also explains the low rumored Battlemage EU numbers by the way.

 

[igor_kavinski]

Intel's 15th gen Lunar Lake architecture leaks with Lion Cove+ P-cores, Xe2 iGPU, and possible lack of Hyperthreading

The Intel Lunar Lake CPUs which are said to debut sometime in 2024/H1 2025 will follow in the footsteps of the Meteor Lake and Arrow Lake chips and pack discreet CPU, GPU, and SoC tiles. Now, new leaks allege that the LNL’s GPU tile features Intel’s next-gen Battlemage graphics with Xe2 cores.

www.notebookcheck.net

The leaker also mentions that the LNL processors may not get “working Rentable Units” that are expected to appear in Arrow Lake chips.

What's a dang rentable unit? Is Intel going to try to put some instructions or even whole CPU blocks behind a subscription based paywall on client CPUs????

 

[Geddagod]

The only leaker that mentioned anything about rentable units is MLID soooo.....
And notebook check got even that wrong, MLID didn't claim rentable units will be in ARL lol

 

[Geddagod]

As said 10nm SF has been renamed Intel 7 and is already in use in RPL, that was stated in a slide from Intel, otherwise RPL-S wouldnt have only 2-3% better perfs.

Intel Raptor Lake-S: Mehr Kerne, Takt und TDP für (viel) mehr CPU-Leistung

Ein „signifikant verbesserter Fertigungsprozess“ soll Raptor Lake von Intel Beine machen und gegen AMD Ryzen 7000 bestehen lassen.

www.computerbase.de

What is that slide supposed to show?
10SF is what's in Tiger Lake
10ESF/Intel 7 is what is in Alder Lake, with a 10-15% perf/watt improvement
That slide shows Intel 7 Ultra (what's used in RPL), and the 'faster raptor cove' core is a combination of both Intel 7 ultra and tweaks in RPC vs GLC itself.

Look, here's a slide that shows that Intel 10SF and Intel 7 are clearly different

 

[Abwx]

What is that slide supposed to show?
10SF is what's in Tiger Lake
10ESF/Intel 7 is what is in Alder Lake, with a 10-15% perf/watt improvement
That slide shows Intel 7 Ultra (what's used in RPL), and the 'faster raptor cove' core is a combination of both Intel 7 ultra and tweaks in RPC vs GLC itself.

Look, here's a slide that shows that Intel 10SF and Intel 7 are clearly different
View attachment 83882

Whatever, my point was that there s no new enhancement of the process used for RPL, next refresh will use the same process given that the perf improvement is tiny if we are to believe the recent leak, and your classification is indeed also in the slide i posted since it state that it s the third gen.

 

[Doug S]

They always have something that starts with A, but seem to name the derivatives differently. Like the TGL 8c started at P or something. Likewise for the ADL 6+0 die.

And you definitely can't pull off a full layer stepping in a couple of weeks. Even if you taped out instantly (which is impossible, as it takes weeks to get the design finalized, masks made, etc.), it takes about a full quarter to get first silicon out of the fab. And that assumes you're paying a fortune for TSMC ultra-mega-super-hot lots (name barely an exaggeration).

A couple weeks may be an exaggeration, but Intel was not limited by the speed of TSMC's hot lots. They could have much "hotter" lots than TSMC since they didn't have any other customers to worry about. That's the whole reason they adopted a more 'try it and see' approach than those who relied more on simulation to verify their designs because they used foundries that had other companies and were limited in how fast a single customer's hot lot could pushed through the fab in front of other customers.

 

[ondma]

Disagree.
Alder Lake and Raptor Lake were good player, however, they beat competitor at ~250W power consmption.
Without saying, 250W SKU is small and small market in the real world.

Especially, RPL relatively lacks competitiveness at ~35W power consmption, gpu computing and so on.
35W SKU is mainstream. So I consider MTL & ARL as hopeful successors.

Lastly, this is a topic that has already been discussed.
You should read old messages over again.

At least AL and RL are competitive at some point. From the leaks so far, it appears ARL will not be competitive at higher power, so how does it follow that it will be somehow magically be competitive or better at lower power? (Yes, I know it is theoretically possible, depending on the characteristics of the node, but until I actually see it in hard data, that just seems like wishful thinking.)

 

[SiliconFly]

Without the mediocre GDDR6 memory controller, PCIe overhead and rBAR struggle we will finaly see the real IPC gains compared to Xe LP. Alchemist(+) tGPU should do much better than the dGPU version unless bandwidth limitation on DDR5/LPDDR5 is a big issue.

Since the tGPU is gonna be tied up with DDR5 (due to lack of GDDR6). there's definitely going to be some memory bandwidth limitation.The tGPU will definitely be better than the older Xe LP. But might not catch up with the dGPU. Or best case might just match it. Won't be better i think.

 

[SiliconFly]

I have no marketing experience. Also I have no interest in it.
In the fact, ADL&RPL brought regaining market share in some country (e.g. Japan) to Intel as 250W SKU.
So I simply consider ADL&RPL were good player and had better competitiveness (c.f. Rocket Lake).

IMO, when we think about competitiveness, we should see things in from a broad perspective, but not in from the details.

Saying ADL & RPL are "good" players is a huge understatement.

They beat the c**p out of Zen series processors worldwide. Before ADL, AMD had a client (Desktop+Laptop) cpu market share of around 22%. Now, it's just at 12% according to Mercury Research.

Meaning, Intel's client cpu market share was down to 78% after successive (14+++++++ & 10+++++) failures. And after ADL & RPL, it's now back to 88%. I think it's phenomenal considering ADL & RPL aren't really that amazing cpus.

If Intel manages to make a splash with MTL, AMD is gonna have very tough times ahead.

 

[SiliconFly]

What aficionados? There is not a single voice here that is pro-Intel. None of the discord servers or subreddits that I frequent could be classified as pro-Intel either. If the roles were reversed, the internet would be concerned with pure performance regardless of efficiency. I see people pairing a 7800X3D and a 7900 XTX all of the time and then boasting about the efficiency of their CPU despite the fact that their choice in GPU offsets it.

The past 2 generations the mantra has been all about power efficiency, core area and the chiplet packaging. All of which are a performance hindrance for a client desktop platform and is configured this way as a consequence of targeting data center and hyperscaler clients. The desktop parts would have decisively outperformed RPL in raw performance if they didn’t have these constraints and were designed from scratch targeting client.

Edit: Thinking about this more, the internet hates Nvidia’s Ada Lovelace cards for the same reason they favor Ryzen. The Ada Lovelace line is class leading with its incredible area and power efficiency. They also are very good at re-using their gaming / enthusiast dies for revenue in workstation / data center. Nvidia’s big margins and silicon efficiency makes their cards hated and considered a bad value / rip-off to enthusiasts. Yet these same principles makes Ryzen great and consumers are happy to contribute to AMD’s big margins.

It's human nature. People always root for the underdog regardless of reason. But thats all set to change very soon with MTL.

 

[SiliconFly]

They're both embarrassing for Intel. SPR is just so bad that it single-handedly shifts the Overton window. At basically any other company, RPL would be an A-step PRQ, and SPR B-step, C at worst.

And that "experimentation" costs how many millions of dollars and months of development per tapeout? There's really no excuse for that poor quality, and I'd argue that Intel's future as a chip designer depends on fixing it.

They're fixing is real fast. Dis-aggregation. Tiles.

 

[SiliconFly]

Intel 7 is 10nm SF renamed.

Nope. Intel 7 is ESF.

ESF is a much improved version of SF. It's like TSMC N5 -> N4

 

[H433x0n]

I would be very surprised if Intel couldn't even boot client A-step silicon.

Intel client chips seem to be averaging around 3 steppings for anything decently complex. ADL took that many, and MTL is on C step as well, iirc. Though tough to say these days without a per-die breakdown, and without knowing the fab situation. Though even RPL took two steppings, which is just embarrassing. AMD, Nvidia, and Apple all regularly ship on A-step.

That's not necessarily true, I think it'd be extraordinarily difficult to get any modern CPU to be in shippable state while still on A-stepping silicon. AMD is still very efficient managing to ship on B-stepping which is very difficult to do on a CPU.

Intel:
13900K - B0 stepping
12900K - C0 stepping (Intel's first mainstream heterogeneous CPU)
11900K - B0 stepping

AMD:
7950X - B2 stepping
5950X - B0 stepping
3950X - B0 stepping

Nvidia - ruled by Jensen's iron fist and they always ship on A-stepping (also it's easier to ship a GPU on A-stepping compared to a CPU)
RTX 4090 - A1 stepping
RTX 3090 - A1 stepping
RTX 2080 Ti - A1 stepping
GTX 1080 Ti - A1 stepping

 

[SpudLobby]

What aficionados? There is not a single voice here that is pro-Intel. None of the discord servers or subreddits that I frequent could be classified as pro-Intel either. If the roles were reversed, the internet would be concerned with pure performance regardless of efficiency. I see people pairing a 7800X3D and a 7900 XTX all of the time and then boasting about the efficiency of their CPU despite the fact that their choice in GPU offsets it.

The past 2 generations the mantra has been all about power efficiency, core area and the chiplet packaging. All of which are a performance hindrance for a client desktop platform and is configured this way as a consequence of targeting data center and hyperscaler clients. The desktop parts would have decisively outperformed RPL in raw performance if they didn’t have these constraints and were designed from scratch targeting client.

Edit: Thinking about this more, the internet hates Nvidia’s Ada Lovelace cards for the same reason they favor Ryzen. The Ada Lovelace line is class leading with its incredible area and power efficiency. They also are very good at re-using their gaming / enthusiast dies for revenue in workstation / data center. Nvidia’s big margins and silicon efficiency makes their cards hated and considered a bad value / rip-off to enthusiasts. Yet these same principles makes Ryzen great and consumers are happy to contribute to AMD’s big margins.

One thing that's worth noting is the overlap between Intel and AMD fans today and 5-10 years ago is almost certainly high. I suspect some of the most annoying AMD fans were at one point huge team blue fans, to make that concrete. In other words he's likely right if Intel were ahead in Perf/Watt again - competitive once more - you'd probably see a bit of a migration of sorts and probably some bashing from blue @ red. However, now that AMD is where it is today, I don't think we'll see remotely we did in the past RE: the asymmetries again and suspect there's a sticky factor, only directionally if that happens.

Yeah, I agree on Nvidia in general terms. The hate for Nvidia is outrageously funny.

 

[SpudLobby]

That's not necessarily true, I think it'd be extraordinarily difficult to get any modern CPU to be in shippable state while still on A-stepping silicon. AMD is still very efficient managing to ship on B-stepping which is very difficult to do on a CPU.

Intel:
13900K - B0 stepping
12900K - C0 stepping (Intel's first mainstream heterogeneous CPU)
11900K - B0 stepping

AMD:
7950X - B2 stepping
5950X - B0 stepping
3950X - B0 stepping

Nvidia - ruled by Jensen's iron fist and they always ship on A-stepping (also it's easier to ship a GPU on A-stepping compared to a CPU)
RTX 4090 - A1 stepping
RTX 3090 - A1 stepping
RTX 2080 Ti - A1 stepping
GTX 1080 Ti - A1 stepping

So? Apple and Qualcomm ship on A pretty regularly and they still have SoC's on an *annual* cadence with pretty significant IP changes if not process changes more often; further, they still fabricate large dice in the case of Apple. I suspect their mobile lineups for AMD ship on something closer to A stepping as well. Intel's client group is still lazy about simulation and tapeouts relative to their competitors. It's not as bad as the datacenter group whatsoever but we've heard more than enough about the problems they have to know they are in a unique position here.

That 12900K doesn't get a pass for being the first mainstream heterogeneous CPU or anything. It was a generational upgrade with a new microarchitecture, the same way the 5950X -> 7950X was both as a matter of process and the node, and yet (apparently) C0, vs AMD's B2 or B0 with the 3950X -> 5950X. The fact that the 13900K which was relatively mild was B step (didn't know that either) I think just highlights part of the problem.

But I suspect this will change going forward as they'll have to start using industry standard EDA sim tools else they'll be charged for hot lots.

 

[SpudLobby]

The original, MTL-R is ARL-U rumor was from Raichu on Twitter. Bionic just seems to be confirming it.
View attachment 83816
I will say though, I haven't seen anywhere that MTL-R will be on Intel 3. All Raichu said was that it would be on "N-1" and "based on the 1276 series". Seems a bit ambiguous, but it seems like MTL-R would be on Intel 4 rather than Intel 3. Perhaps if it is on Intel 3, however, Intel could be looking to just move their core IP from GNR/SRF over to MTL-R, with some tweaks.

Hmmm. I'd like to see a MTL refresh on Intel 3 and hope they go for it, even if it won't have the ARL IP if they work around a few issues with MTL (apparent issues we will see) and hand it a new process node for the compute tile that could be significant for both energy efficiency and maybe idle draw as well, albeit without the cost structure of N3 or 20A.

 

[Geddagod]

So? Apple and Qualcomm ship on A pretty regularly and they still have SoC's on an *annual* cadence with pretty significant IP changes if not process changes more often; further, they still fabricate large dice in the case of Apple. I suspect their mobile lineups for AMD ship on something closer to A stepping as well.

5800h shipped A0. The 1165g7 shipped B1.

 

[SpudLobby]

5800h shipped A0. The 1165g7 shipped B1.

Ok so that's not awful for Intel but not fantastic. More impressive from AMD I think given that was Ice Lake to Tiger Lake (very minimal CPU IP change in particular though graphics sure), whereas the former was Renoir to Cezanne (major CPU IP change) and both were on a similar process.

 

[SpudLobby]

I think "Intel client design teams aren't much worse than their competitors or other big whig design firms" on tapeouts/steppings etc isn't a hill I'd want to fight on but I think it's true they aren't in the state that the DC team is, e.g. there are real gaps but nothing insane.

Again, this is all irrelevant though seeing as they're about to be charged for hot lots going forward and it seems like Lion Cove is synthesizable and maybe even Redwood Cove depending on the variance between Intel 4 and Intel 3 design rules and the truth value of that MTL Intel 3 refresh rumor (or alternatively they'll make it a PITA on themselves).


So the process and results will be forced to change or else on some level. Or at least they'll have incentive structures between internal fab model and utilization of external foundries.

 

[igor_kavinski]

Always fun to see people play "My stepping is better than yours"