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Discussion Intel current and future Lakes & Rapids thread

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SpudLobby said:

davidbepo (@davidbepo@mastodon.social)

aside from losing well, WELL over 20% in perf this also means ARL gets a node downgrade compared to MTL, its predecessor, which already failed to reach 5 GHz, ARL should regress clocks even further and while i expect IPC here to be better than AMD the massive clock gap and SMT L should mean Zen5...
mastodon.social mastodon.social

Oh man, I figured he would be and sure enough. Bepo is having a meltdown lmao.
Click to expand...
heh, that reminded me to create a mastadon account.
I'm a bit confused about SMT though. I believe that LNC isn't gonna have SMT, but Bepo is claiming LNC has SMT available but won't be used bcuz of bugs? Idk. The difference here between the two scenarios (LNL not having SMT in the first place vs LNL having SMT but not enabling it due to bugs) is pretty big IMO, even if to the end user it's not.
Something else Bepo claimed was that E-cores in LNL were placed off ring. Ik he was hating on the decision, but is this not actually beneficial for what LNL looks like it's going to be? It won't have to share that voltage plane as the P cores, and I'm assuming the E-cores will be able to be used as the "LP" E-cores are being used in MTL SOC tile.
Also the 20A shilling is insane lol. Why does he hate N3E so much?
I'm also half convinced Bepo is trying to reverse jinx Intel or something haha
Still extremely disappointing honestly, would literally have rather seen them do ARL on i3 and actually ship a load of volume, but oh well.
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fr. It's not the best look, but ARL looks to have been planned to dual source for a while, and IMO it's not that big of a deal. GNR is the real deal tho, Intel has no excuses if GNR/SRF ends up behind schedule.
 
Geddagod said:
heh, that reminded me to create a mastadon account.
I'm a bit confused about SMT though. I believe that LNC isn't gonna have SMT, but Bepo is claiming LNC has SMT available but won't be used bcuz of bugs? Idk. The difference here between the two scenarios (LNL not having SMT in the first place vs LNL having SMT but not enabling it due to bugs) is pretty big IMO, even if to the end user it's not.
Something else Bepo claimed was that E-cores in LNL were placed off ring. Ik he was hating on the decision, but is this not actually beneficial for what LNL looks like it's going to be? It won't have to share that voltage plane as the P cores, and I'm assuming the E-cores will be able to be used as the "LP" E-cores are being used in MTL SOC tile.
Also the 20A shilling is insane lol. Why does he hate N3E so much?
I'm also half convinced Bepo is trying to reverse jinx Intel or something haha

fr. It's not the best look, but ARL looks to have been planned to dual source for a while, and IMO it's not that big of a deal. GNR is the real deal tho, Intel has no excuses if GNR/SRF ends up behind schedule.
Click to expand...
N3E itself looks quite impressive and there's no revealed detailed information for 20A's difference between Intel 4 and Intel 3, nor 20A difference compared with 20A PowerVia. Just hoping supply would still not be an issue for Intel overall.
 
SpudLobby said:

davidbepo (@davidbepo@mastodon.social)

aside from losing well, WELL over 20% in perf this also means ARL gets a node downgrade compared to MTL, its predecessor, which already failed to reach 5 GHz, ARL should regress clocks even further and while i expect IPC here to be better than AMD the massive clock gap and SMT L should mean Zen5...
mastodon.social mastodon.social

Oh man, I figured he would be and sure enough. Bepo is having a meltdown lmao.
Click to expand...
Lmao, this is hilarious. Funny thing is, I kinda agree with the first half or so... right up until he starts talking about ARL/LNL. Then he goes full wacko.

Remember, this is the guy that claimed that Intel 4 would top out at 4.6GHz. Even MTL will comfortably beat that. He has a weird obsession with irrelevant process details. And that's not even touching on his architectural claims...
 
Geddagod said:
I'm a bit confused about SMT though. I believe that LNC isn't gonna have SMT, but Bepo is claiming LNC has SMT available but won't be used bcuz of bugs?
Click to expand...
Client LNC, if nothing else, doesn't have SMT period. Server, if it even exists at all, I don't know. Maybe they could enable it in another stepping, but it's not being disabled for funsies.
Geddagod said:
Something else Bepo claimed was that E-cores in LNL were placed off ring. Ik he was hating on the decision, but is this not actually beneficial for what LNL looks like it's going to be? It won't have to share that voltage plane as the P cores, and I'm assuming the E-cores will be able to be used as the "LP" E-cores are being used in MTL SOC tile.
Click to expand...
Yeah, if true, that seems to be an extension of the MTL LP E-core concept, just on a monolithic-ish die. You can have separate voltage rails for P-cores and E-cores on the same fabric, though, so that's not it. The main advantage I can see is the ability to shut down the ring but still leave some compute active. And if they really go crazy, that particular cluster could have it's own voltage rail.

As for latency, bandwidth, etc. I'm not seeing any inherent compromise there. If anything, you'd think memory latency would be better.
Geddagod said:
fr. It's not the best look, but ARL looks to have been planned to dual source for a while, and IMO it's not that big of a deal. GNR is the real deal tho, Intel has no excuses if GNR/SRF ends up behind schedule.
Click to expand...
GNR/SRF might be more important to Intel in the short term, but I do think any setback with 20A is a huge problem. Everyone's looking at it to gauge the health/timeline of 18A, which will not only be important to Intel's own products, but will be their foundational IFS node as well. They need to prove themselves with real silicon, not just slideshows.
 
Exist50 said:
Lmao, this is hilarious. Funny thing is, I kinda agree with the first half or so... right up until he starts talking about ARL/LNL. Then he goes full wacko.

Remember, this is the guy that claimed that Intel 4 would top out at 4.6GHz. Even MTL will comfortably beat that. He has a weird obsession with irrelevant process details. And that's not even touching on his architectural claims...
Click to expand...
Oh yeah, he’s crazy. It’s hilarious, this is nutty exaggeration and the phrasing is an unintended bit. I want to say it’s a skilled gag but I know better.

The implication about N3E in 2025 being worse than Intel 4 out of the gate though is icing on it all.

Agree on first half at parts vs later. For instance the pure foundry idea I’d prefer for Intel’s future to the other way around.
 
Geddagod said:
Something about use of copper metal layers for Intel 4 right? I don't remember.
My favorite Bepo moment is when he was claiming Intel sabotaged SPR on purpose.
Click to expand...
It’s legitimately hilarious to me. The phrasing too tops it off, he really is an unintended entertainer.

I love how much he loves Intel 7. I think he’d use it for the next 3 years if he could save for a mature 20A/18A. Just going straight from FinFET 7NM HP Cobalt DUV cancer to GaaFETs, EUV, backside power delivery.

Something insanely funny about all this.
 
Exist50 said:
Yeah, he was livid that they dropped Cobalt.
https://twitter.com/x/status/1521492211426377729

View attachment 83083
Click to expand...
muh cobalt. God this is so funny. He really, really loves his mediocre yield insane clock Intel 7.

Didn’t they come up with a cobalt coated copper anyways with a good improvement upon both cobalt and copper alone? Idk why he’s complaining.

Edit: oh holy [redacted] at him throwing literal clock walls for the entire process like that off early yield estimations as if fact of the matter in a technical sense. Lmao @ i3 capped at 5.1 and the hierarchy he has going on based off this absolute maximum switching potential.
 
Exist50 said:
Client LNC, if nothing else, doesn't have SMT period. Server, if it even exists at all, I don't know. Maybe they could enable it in another stepping, but it's not being disabled for funsies.

Yeah, if true, that seems to be an extension of the MTL LP E-core concept, just on a monolithic-ish die. You can have separate voltage rails for P-cores and E-cores on the same fabric, though, so that's not it. The main advantage I can see is the ability to shut down the ring but still leave some compute active. And if they really go crazy, that particular cluster could have it's own voltage rail.

As for latency, bandwidth, etc. I'm not seeing any inherent compromise there. If anything, you'd think memory latency would be better.

GNR/SRF might be more important to Intel in the short term, but I do think any setback with 20A is a huge problem. Everyone's looking at it to gauge the health/timeline of 18A, which will not only be important to Intel's own products, but will be their foundational IFS node as well. They need to prove themselves with real silicon, not just slideshows.
Click to expand...
Agreed with everything here.
 
1689507569211.png
just to add my comment: If I had to guess, I'm assuming Xino is referring to 'old day l2' as the l2s that were the size of 256 or 512KB.
 
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So, a 4th cache layer, but instead of naming it in order 1>2>3>4, it's named 0>1>2>3.
Kinda logical move tbh, as L1 capacity has barely moved from Core 2 Duo days. but L2 has increased by 8X from the first Core i chips.
Would still prefer intel to stick to 1>2>3>4 naming though.
 
Exist50 said:
Those charts are garbage. They're likely just doing some sort of highly naive extrapolation. If Intel 3 was competitive with N3, Intel would be using it instead.
Click to expand...

While I don't disagree that without some sourcing those charts are at best educated guesses, there are several possible reasons why Intel might use N3E instead of Intel 3 even if the latter was competitive:

1) they have a contract with TSMC requiring them to buy a certain number of N3 wafers...if so they gotta use them on something
2) Intel lacks sufficient Intel 3 capacity
3) Intel 3 chips, when working properly, are competitive but Intel 3 yields aren't where they need to be

I imagine others might come up with some additional reasons to add to the list.
 
Doug S said:
While I don't disagree that without some sourcing those charts are at best educated guesses, there are several possible reasons why Intel might use N3E instead of Intel 3 even if the latter was competitive:

1) they have a contract with TSMC requiring them to buy a certain number of N3 wafers...if so they gotta use them on something
2) Intel lacks sufficient Intel 3 capacity
3) Intel 3 chips, when working properly, are competitive but Intel 3 yields aren't where they need to be

I imagine others might come up with some additional reasons to add to the list.
Click to expand...
If they are producing Intel 3 for GNR and SRF, I think yields should be good enough to produce desktop chips as well. Both are slated for a 2H 2024 (GNR and ARL). I agree with 1 and 2 though.
 
Geddagod said:
If they are producing Intel 3 for GNR and SRF
Click to expand...

Figure until they spin off the fabs, they will keep producing the main server die internally. Has nothing to do about their confidence in the nodes themselves. I think that's a line they won't cross.

I imagine the IO die will be fabbed at TSMC but I don't think there's been confirmation on what node they are using.
 
S'renne said:
N3E itself looks quite impressive
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It shit.
Barely better than newer N4 derivatives and with no SRAM scaling a lot of designs get very low ROI on it.
Makes sorta-tangible sense in mobile where a like 10-15% efficiency bump matters and favela chips like Turin-Dense and not really anywhere else (for now).
mikk said:
It really seems like Lion Cove will come with more changes than usual
Click to expand...
Yea it's a big one.


no profanity in the tech forums

esquared
Anandtech Forum Director
 
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Geddagod said:
If they are producing Intel 3 for GNR and SRF, I think yields should be good enough to produce desktop chips as well. Both are slated for a 2H 2024 (GNR and ARL). I agree with 1 and 2 though.
Click to expand...
So we even know how many fabs/wafers Intel is producing for I3? I thought it was one FAB. I thought that I4 and I18a were being built out allot, but I3 and I20a were more like transitional nodes. Actually, since Intel's server CPUs were moved from I4 to I3, I would think it would be more than one FAB - unless their projected server CPU sales are really in the tank.

Please correct me - I'm sure I am wrong.
 
www.igorslab.de

Intel’s internal performance projection for Raptor Lake S Refresh and Arrow Lake S - How fast the CPU and iGP are expected to be | Exclusive | igor´sLAB

The Raptor Lake refresh is expected to arrive this year as the 14th CPU generation for the desktop. But the real successor, Arrow Lake-S for desktop, is also increasingly materializing along with the…
www.igorslab.de www.igorslab.de

You will buy Granite Ridge because you will buy Granite Ridge.
Because I've said so.
Image-02.jpg
 
Last edited:
adroc_thurston said:
www.igorslab.de

Intel’s internal performance projection for Raptor Lake S Refresh and Arrow Lake S - How fast the CPU and iGP are expected to be | Exclusive | igor´sLAB

The Raptor Lake refresh is expected to arrive this year as the 14th CPU generation for the desktop. But the real successor, Arrow Lake-S for desktop, is also increasingly materializing along with the…
www.igorslab.de www.igorslab.de

You will buy Granite Ridge because you will buy Granite Ridge.
Because I've said so.
Image-02.jpg
Click to expand...
Somehow we can get internal performance projections but still can’t get a straight answer about what node will be used for different parts of the product stack.
 
www.igorslab.de

Intel’s internal performance projection for Raptor Lake S Refresh and Arrow Lake S - How fast the CPU and iGP are expected to be | Exclusive | igor´sLAB

The Raptor Lake refresh is expected to arrive this year as the 14th CPU generation for the desktop. But the real successor, Arrow Lake-S for desktop, is also increasingly materializing along with the…
www.igorslab.de www.igorslab.de

Apparently clocks are shit. 5 bucks it's because Intel tried using HD cells with TSMC 3nm and couldn't get clocks up lol.
IPC uplift actually seems to be decent, bcuz apparently ARL-S isn't going to clock very well... around MTL levels.
Cache changes are supposed to bring greater than expect gaming perf uplifts though ¯\_(ツ)_/¯
Somehow we can get internal performance projections but still can’t get a straight answer about what node will be used for different parts of the product stack.
Click to expand...
ARL looks to be in a ... unique? situation lol



No profanity in the tech forums.


esquared
Anandtech Forum Director
 
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