Discussion Intel current and future Lakes & Rapids thread

[H433x0n]

There is no conversation, Intel's best core in years is completely mid in terms of PPA, both in mobile and desktop.
All while Pat is burning obscene amounts of cash on fabs.

It’s cool to have preferences for a brand, I just don’t get how it turns into passionate dislike for another corporation. It’s some weird online phenomenon I haven’t figured out.

I don’t even get this excited when I see the New Orlean Saints do poorly and they’ve embarrassed my team for years.

 

[S'renne]

Intel’s internal performance projection for Raptor Lake S Refresh and Arrow Lake S - How fast the CPU and iGP are expected to be | Exclusive | igor´sLAB

The Raptor Lake refresh is expected to arrive this year as the 14th CPU generation for the desktop. But the real successor, Arrow Lake-S for desktop, is also increasingly materializing along with the…

www.igorslab.de

Apparently clocks are shit. 5 bucks it's because Intel tried using HD cells with TSMC 3nm and couldn't get clocks up lol.
IPC uplift actually seems to be decent, bcuz apparently ARL-S isn't going to clock very well... around MTL levels.
Cache changes are supposed to bring greater than expect gaming perf uplifts though ¯\_(ツ)_/¯

ARL looks to be in a ... unique? situation lol

Tbh hope there would be changes in develop since it's still way too early to have these performance projections be the finalised results...at least their chiplet tech worked for the iGPU currently lmao

 

[adroc_thurston]

I just don’t get how it turns into passionate dislike for another corporation

I can't like a company that kinda directly rolls me over due to beyond uncompetitive server parts.
I had hopes for LNC and future atoms because that's the fuel of their server roadmap but they are very much in vain.

 

[msj10]

I guess the poor ST is from a big clock speed regression but is that because of N3 clocking badly or from the core itself being designed for lower frequency to improve area?

 

[adroc_thurston]

but is that because of N3 clocking badly

Not really, the node is OK, just meh yields.

the core itself being designed for lower frequency to improve area

Mostly this yes.

 

[coercitiv]

I don’t see a 4-6% ST improvement worthy of justifying the money spent on the packaging and marketing material.

A blast from the past:

The Anandtech Haswell Review

In general, I saw performance gains over Ivy Bridge of 1 - 19%, with an average improvement of 8.3%.

 

[H433x0n]

A blast from the past:

The Anandtech Haswell Review

Those were on the same node. This is supposed to be 2 full node jumps. It’s historically bad in that context.

It should be scrapped and everything shifts to a MTL refresh since that should have better perf/w than what is in that data.

 

[yuri69]

A blast from the past:

The Anandtech Haswell Review

Correct me if I'm wrong, but Haswell improved a bit when SW caught up with AVX2 & friends.

As for the Arrow, they still have time to tune the frequency via a respin or two.

 

[Henry swagger]

It’s cool to have preferences for a brand, I just don’t get how it turns into passionate dislike for another corporation. It’s some weird online phenomenon I haven’t figured out.

I don’t even get this excited when I see the New Orlean Saints do poorly and they’ve embarrassed my team for years.

Well said

 

[coercitiv]

Those were on the same node.

Tick-tock, remember? Back then, same node (theoretically) meant bigger architectural changes. Zen 3 was on the same node.

With just one internal slide you went from extremely bullish on Intel to grumpy bear mode. We have plenty of time for either until 2024, or even until 2025.

Correct me if I'm wrong, but Haswell improved a bit when SW caught up with AVX2 & friends.

AVX2 was of little consequence for consumers at the time. Haswell's biggest strength against Ivy was in mobile, it lowered idle power consumption to much lower levels.

As for the Arrow, they still have time to tune the frequency via a respin or two.

We don't know what these internal projections are factoring in already, the respins may be accounted for.

Anyway, my (stealth) point was that arguing ARL should not be made anymore seems like an emotional reaction. Intel has an execution schedule, they need to deliver on time. Smaller gains but fast iteration is something Intel has to master if they're going to get back on track. I've been saying a couple of times now that wishing for a C2D moment is not compatible with reality. Intel will have to fight for every inch.

Maybe when we get 65W and 125W performance estimates the mood around here will change for the better. If the problem is indeed related to node performance scaling, then performance scaling at much lower power levels should be a different story.

 

[Khato]

Maybe when we get 65W and 125W performance estimates the mood around here will change for the better. If the problem is indeed related to node performance scaling, then performance scaling at much lower power levels should be a different story.

Indeed, too bad it wasn't the 65W estimates that got leaked.

Another important point to keep in mind is that the performance projections are only reporting PL1/PL2 values, not actual power consumption. And it doesn't look like the frequencies were included in the leak either which would provide further insight.

 

[poke01]

everyday Intel proves that Apple leaving was for good reason.
If Arrow lake is only a up to 21% uplift from RPL refresh then oh boy. new node, brand new core design.

We will see how Apple and AMD respond. heres hoping Lunar is good

 

[uzzi38]

everyday Intel proves that Apple leaving was for good reason.
If Arrow lake is only a up to 21% uplift from RPL refresh then oh boy. new node, brand new core design.

We will see how Apple and AMD respond. heres hoping Lunar is good

Lunar is interesting because of the changes made around the core more than the cores themselves. I mean, I'm sure they'll also be better tuned for low power, but the star of the show really should still be elsewhere.

 

[davidbepo]

Lmao, this is hilarious. Funny thing is, I kinda agree with the first half or so... right up until he starts talking about ARL/LNL. Then he goes full wacko.

Remember, this is the guy that claimed that Intel 4 would top out at 4.6GHz. Even MTL will comfortably beat that. He has a weird obsession with irrelevant process details. And that's not even touching on his architectural claims...

fun ARL is a confirmed clock regression over MTL, and it barely improves perf by intels own admision
BTW hilarious how you use my old MTL number and not the new one:

https://twitter.com/x/status/1666180008723791873

 

[Exist50]

fun ARL is a confirmed clock regression over MTL

It is not. Vs RPL, most likely, but there's no evidence yet of a regression vs MTL. To say nothing about the entirely different cores.

BTW hilarious how you use my old MTL number and not the new one

Then by all means give your new ones. I haven't seen any other than what's posted here.

Is your strategy to make a bunch of wild guesses and ignore all the wrong ones? Because you sure seem intent on sweeping your wildly off base predictions under the rug.

 

[davidbepo]

It is not. Vs RPL, most likely, but there's no evidence yet of a regression vs MTL. To say nothing about the entirely different cores.

Then by all means give your new ones. I haven't seen any other than what's posted here.

Is your strategy to make a bunch of wild guesses and ignore all the wrong ones? Because you sure seem intent on sweeping your wildly off base predictions under the rug.

i edited it with link, took a bit to find it because i archived my twitter
also are you claiming LNC is a 8% IPC uplift over RWC or what LMAO

 

[Exist50]

i edited it with link, took a bit to find it because i archived my twitter

Great, you made this easy. Still wrong. Will look forward to seeing if you follow through with that "bet".

also are you claiming LNC is a 8% IPC uplift over RWC or what LMAO

Where did you get 8% from?

 

[davidbepo]

btw yall need a serious dose of R E A D

davidbepo (@davidbepo@mastodon.social)

and about ARL well ive saved the best(worst) for the last, as said above SMT has been disabled, even tho apparently the core still supports it, this will more than negate any MT IPC uplift since SMT yield was about 30% before and IPC uplift is below that, but that isnt the biggest downgrade, no...

mastodon.social

i didnt say outright they disabled it, just that thats the case AFAIK, LNC may be SMT less by design, and all the same arguments would apply

 

[davidbepo]

Great, you made this easy. Still wrong. Will look forward to seeing if you follow through with that "bet".

Where did you get 8% from?

oh noes its 4,8 instead of 4,7 ha, im still right
8% is roughly what IPC would need to be for it to perf as it does without a clock regression, which is definitely not the case, this is gonna trail mobile TGL LMAO

 

[Exist50]

btw yall need a serious dose of R E A D

davidbepo (@davidbepo@mastodon.social)

and about ARL well ive saved the best(worst) for the last, as said above SMT has been disabled, even tho apparently the core still supports it, this will more than negate any MT IPC uplift since SMT yield was about 30% before and IPC uplift is below that, but that isnt the biggest downgrade, no...

mastodon.social

i didnt say outright they disabled it, just that thats the case AFAIK, LNC may be SMT less by design, and all the same arguments would apply

Are you seriously hiding behind the word "apparently"?

 

[davidbepo]

Are you seriously hiding behind the word "apparently"?

dont blame me for your poor reading comprehension, the word is there for a reason, now i do believe it is disabled but really its the same for all purposes otherwise

 

[Exist50]

oh noes its 4,8 instead of 4,7 ha, im still right

Keep going...

It's funny how many times you have to change your "totally correct" numbers.

Anyway, happy to check back on your projections in a couple of months, with some popcorn in tow.

 

[moinmoin]

They’re going to pivot to something else.

Intel traditionally is very good at filling their product range with different core gens that all at least decently serve the respective markets. They will try to do that with coming gens as well.

Intel's biggest competitive advantage against AMD hasn't been performance (which only really matters in high end, everything else is nerfed anyway) but quantity, and I expect Intel to deliver at least that in the future as well.

 

[mikk]

Only 10% SC uplift, for real? It can't be just 10% IPC uplift.....maybe there is a big peak clock speed regression from 6 Ghz to like 5.5 Ghz or even lower. MT performance looks better to me if there is no SMT. Without SMT they are losing like 20% performance in some of the better multithreaded benchmarks. It's a mediocre improvement however considering it uses Lion Cove+Skymont+3nm.

 

[JoeRambo]

That L0-L1-L2-L3 change is real strange, i don't quite get it.

The old ( Nehalem to Skylake ) scheme was the following:

small but fast 256KB L2 inclusive in L3 cache.
L3 cache that had varied performance, but while it had low inter core latency it suffered from cross core pollution of L3 cache etc and Skylake-X server variant already switched to non inclusive L3 ( with disaster level of L3 performance, anemic in size and horrible latency/bw ).
Cloud guys loved the new server L3 scheme, cause workloads were mostly contained in L2 and L3 cross pollution was no longer consideration in predictable perf. Said cloud guys moved on to love AMD's Z3 chiplets even more as it had actually functional L3 instead.

Nowadays we have the following:

So for client Intel came up with idea of enlarging L2 ( costs quite some latency ), making it no longer inclusive in L3. L3 is still a very weak point on client ( too little size, high latency, low bw ). On server it is full on disaster, reaching 50ns latency, clearly a design by idiots supervised by morons.

So instead of fixing L3 cache, they are throwing in additional level of caching? It probably does not take a rocket scientist, but i feel like the "new L2" is like AMD's L3 -> shared by core complex of 4 or maybe even 8? And then there is "the new L3" that serves the whole SoC.

It could work, Apple's SoCs are something like that.

So it would look like this:

L1 => 48KB of data cache
L2 => 256kb or 512kb INCLUSIVE in L3
L3 = > some 4-8MB per core, Apple has 16MB of L2 shared by perf core complex
L4 => most likely no longer "sliced" but rather served by SoC as system level cache, maybe even on different chip, 3D stacked, why not

Would make Apple/AMD like chip. If 8C perf complex with 32MB of L3 sounds familiar, well it's cause likely quite some of us are reading this on it today.

What i don't quite understand is how it would fix Intel's server pains unless they are going full chiplet route. Or stop designing server CPUs. Tho considering their recent "performance" i would not be suprised by another abomination where L3 caches actually hurt performance most of the time.


P.S. The more i think about it: this whole "L0 naming scheme" is inflicted by Intel's byzantine internal corporate politics and marketing idiots, who after realizing that it's basically carbon copy of AMD's chiplets, went on to obfuscate things with "L0 level" of caching.