Discussion Intel current and future Lakes & Rapids thread

[SteinFG]

meaning they'll have a lot to make up for in IPC when core count and frequency come down with 15th gen

Cores won't come down. i9 15900 will mostlikely be 8+16, i5 15500 will most likely be 6+8
And we don't know the freq. of 15th gen (arrow lake), it might be on par, becuase intel will use TSMC N3 to produce desktop chips.

 

[H433x0n]

Well there is it. That's Raptor Lake Refresh and it makes perfect sense. More cores down the stack and more frequency at the top of the stack.

Intel is setting the bar pretty high as far as core count and frequency for 15th gen though... meaning they'll have a lot to make up for in IPC when core count and frequency come down with 15th gen.

I'm not sure if we'll see a 14600K that is 8P+8E, I think that's just an extrapolation from the "leaker" RGT. I wouldn't rule it out, but I haven't seen anything about that from somebody I consider reputable.

There is credible information for a mobile 14650HX that is 8P+8E & 14500HX that is 6P+8E; However, that is a mobile SKU so I'm not sure if that will translate to desktop. If I had to do a guess, I could see that carrying over to desktop where they introduce a "14650K" but that's not something I'd bet any money on.

 

[SpudLobby]

So we've discussed Lunar Lake being on N3.

But more interestingly and I think only lightly touched here is that apparently the entirety of Arrow Lake - including mobile - will now be N3 only.

Second link, explicitly claiming 20A ARL tile is canned.

@H433x0n recall our conversation on Intel claiming "manufacturing ready" and the importance of that whole "actually yielding quality silicon with high volume" thing? Keep in mind this isn't even a particularly high bar, it's nothing like the kind of quality yields, volume and dice TSMC usually pumps in that first year for Apple. So now we're quite possibly if not likely looking at not only no client DGPUs or iGPU tiles on i4/i3/20A, and now no ARL at all - not just mobile - on 20A.

Also again highlights how PowerVIA and Backside Power Delivery alone doesn't mean enough - even LNL on N3 highlights that and should make you question your previous opinion on 20A and 18A.

I won't claim this is definitive proof - it's a rumor, but I am not inclined to reflexively doubt this rumor seeing the sources and knowing the existing rumors and the directions they point to. This is just a step further.



Mind you, I don't like seeing this. Would rather just be wrong.

 

[S'renne]

So we've discussed Lunar Lake being on N3.

But more interestingly and I think only lightly touched here is that apparently the entirety of Arrow Lake - including mobile - will now be N3 only.

Second link, explicitly claiming 20A ARL tile is canned.

@H433x0n recall our conversation on Intel claiming "manufacturing ready" and the importance of that whole "actually yielding quality silicon with high volume" thing? Keep in mind this isn't even a particularly high bar, it's nothing like the kind of quality yields, volume and dice TSMC usually pumps in that first year for Apple. So now we're quite possibly if not likely looking at not only no client DGPUs or iGPU tiles on i4/i3/20A, and now no ARL at all - not just mobile - on 20A.

You have to read between the lines, paper nodes being available don't mean anything particularly where we know recent results have been poor and clients are few and far. The entire point of a foundry is, you know, the whole revenue thing via mass market silicon, true even internally. It's not an 8th grade science fair. Also again highlights how PowerVIA and Backside Power Delivery alone doesn't mean anything - even LNL on N3 highlights that and should make you question your previous opinion on 20A and 18A.

I won't claim this is definitive proof - it's a rumor, but I am not inclined to reflexively doubt this rumor having followed the sources and knowing the existing rumors and the directions they point to. This is just a step further.

Will be interesting to see where their server parts go, and also when (God forbid it gets to "if" but I don't think so...) we'll get an Intel client product on IFS' i4 or newer nodes, save for MTL. Frankly, Intel 3 having HD cells means I'd love to see them do something lower cost, lower power with that, even an MTL refresher of some kind, but they won't.

Mind you, I don't like seeing this. Would rather just be wrong.

That's not good...20A was emphasized as Intel with PowerVia to compete with TSMC N3 right? And if everything is on TSMC wouldn't supply be as tight as AMD then?

 

[SpudLobby]

That's not good...20A was emphasized as Intel with PowerVia to compete with TSMC N3 right? And if everything is on TSMC wouldn't supply be as tight as AMD then?

Maybe but probably not, Intel has very obviously paid up and made some wafer commitments with legroom for this scenario and the fact that they’ll be on N3 before AMD’s mobile lineup somewhat highlights that.


It’ll be fine. N5 being so good and N3 cost takes some load off of demand I believe.

 

[S'renne]

Maybe but probably not, Intel has very obviously paid up and made some wafer commitments with legroom for this scenario and the fact that they’ll be on N3 before AMD’s mobile lineup somewhat highlights that.


It’ll be fine. N5 being so good and N3 cost takes some load off of demand I believe.

I mean every major tech company from phones, to laptops and PCs would soon be on N3 that's why I was worried in supply issues...

 

[H433x0n]

So we've discussed Lunar Lake being on N3.

But more interestingly and I think only lightly touched here is that apparently the entirety of Arrow Lake - including mobile - will now be N3 only.

Second link, explicitly claiming 20A ARL tile is canned.

@H433x0n recall our conversation on Intel claiming "manufacturing ready" and the importance of that whole "actually yielding quality silicon with high volume" thing? Keep in mind this isn't even a particularly high bar, it's nothing like the kind of quality yields, volume and dice TSMC usually pumps in that first year for Apple. So now we're quite possibly if not likely looking at not only no client DGPUs or iGPU tiles on i4/i3/20A, and now no ARL at all - not just mobile - on 20A.

Also again highlights how PowerVIA and Backside Power Delivery alone doesn't mean enough - even LNL on N3 highlights that and should make you question your previous opinion on 20A and 18A.

I won't claim this is definitive proof - it's a rumor, but I am not inclined to reflexively doubt this rumor seeing the sources and knowing the existing rumors and the directions they point to. This is just a step further.



Mind you, I don't like seeing this. Would rather just be wrong.

I don't know enough about the progress of 20A/18A to dispute any of this. I'm skeptical that 20A ARL is being cancelled since it'd absolutely have catastrophic consequences, although I don't take it as a given that 20A/18A will release by EOY 2024. We'll just have to wait and see.

I do know that both Intel 4 and 3 are healthy because I know people working on projects that are going to be fabricated on that process. It's possible that they fumbled 20A/18A since these are different teams working on these projects. The backup plan was Intel 4 /3 with PowerVia, I would personally look for that being productized through the fabs as a leading edge indicator that RibbonFet / GAAFet nodes are in trouble.

 

[Geddagod]

About 20a being cancelled for ARL
Xino leaked that the -H series were being canned on 20a, not all of mobile IIRC. (And I have to go off recall here, since Xino deleted said tweet lol).
I wouldn't automatically assume that this would mean all of mobile is gonna be on N3, since as Raichu speculated earlier, the reason they would be moving 20A products to TSMC 3nm would be so that they could pull in ARL mobile from 1Q 2025 to 4Q 2024. From what I have seen, the H series are usually the first mobile products to launch, with the lower power u/p models coming later, so it wouldn't be too surprising to see those on Intel 20A IMO, esp if Intel is trying to show off the power efficiency of their node.
But that's assuming even the original Xino rumor was correct. Usually for rumors about products far into the future or smaller rumors, I wouldn't be so cautious about it, but for something like this, I would wait for at least one more credible leaker to say something tbh.
If it is true though, that all of mobile is now external, well... at this point I think some of that blame should be shouldered on Pat. One one hand, he might have just decided to focus all their resources on N3 since it might be in development at a better pace than their 20A products, and just didn't want to risk having it delayed, but it's still a terrible look.

 

[Geddagod]

I don't know enough about the progress of 20A/18A to dispute any of this. I'm skeptical that 20A ARL is being cancelled since it'd absolutely have catastrophic consequences, although I don't take it as a given that 20A/18A will release by EOY 2024. We'll just have to wait and see.

I do know that both Intel 4 and 3 are healthy because I know people working on projects that are going to be fabricated on that process. It's possible that they fumbled 20A/18A since these are different teams working on these projects. The backup plan was Intel 4 /3 with PowerVia, I would personally look for that being productized through the fabs as a leading edge indicator that RibbonFet / GAAFet nodes are in trouble.

I'm not going to double down on this, I don't have insider connections after all.
Head cannon, ARL was designed for Intel 3 (or Intel 7nm+) with TSMC 3nm as the contingency plan, both developed in near parallel (which appears to be a common theme with many Intel products since Bob Swan). It would make sense, since Intel usually develops a new arch on the same node, and on a new node usually just ports an old arch over with minimal improvements. At some point, after the original core specs were already in place, Intel saw an opportunity to use Intel 20A due to their delays in their core/CPU development roadmap being worse than the delays in their node roadmap (cough cough meteor lake cough cough). But it looks like that's not going to pay off...
I believe Intel being too aggressive is being corrected again. PTL looks like it's using a diff arch than originally planned for, which I'm guessing is going to be a small LNC+ rather than a completely new arch like what might have been originally planned. GNR might have been been able to get away with using LNC as well rather than RWC+ ( at least from the perf numbers Pat described the GNR core to be as) but it doesn't look like they went for that. And they are completely cutting out a bunch of HPC GPU products, and exiting a bunch of other markets.

 

[msj10]

I think the ARL-S 6+8 die might be the one to use 20A like MLID said.

 

[H433x0n]

I'm not going to double down on this, I don't have insider connections after all.
Head cannon, ARL was designed for Intel 3 (or Intel 7nm+) with TSMC 3nm as the contingency plan, both developed in near parallel (which appears to be a common theme with many Intel products since Bob Swan). It would make sense, since Intel usually develops a new arch on the same node, and on a new node usually just ports an old arch over with minimal improvements. At some point, after the original core specs were already in place, Intel saw an opportunity to use Intel 20A due to their delays in their core/CPU development roadmap being worse than the delays in their node roadmap (cough cough meteor lake cough cough). But it looks like that's not going to pay off...
I believe Intel being too aggressive is being corrected again. PTL looks like it's using a diff arch than originally planned for, which I'm guessing is going to be a small LNC+ rather than a completely new arch like what might have been originally planned. GNR might have been been able to get away with using LNC as well rather than RWC+ ( at least from the perf numbers Pat described the GNR core to be as) but it doesn't look like they went for that. And they are completely cutting out a bunch of HPC GPU products, and exiting a bunch of other markets.

As far as I know, ARL was always destined for the node that came after Intel 4 (it was called 7nm back then). Both MTL & ARL are 'de-risk' products meant to be used as a stepping stone for new process technology coupled with external process nodes. MTL at one point was intended to be a bigger deal than what we ended up receiving. Frankly, if you go back 2 years a lot of product road maps are unrecognizable to what we have today.

I think a lot of people overthink Intel’s use of TSMC processes. There’s a combination of factors involved - existing commitments, volume for cutting edge processes and cost. TSMC’s nodes also happen to be quite good in areas that Intel’s processes sometimes have issues with. Both TSMC and Intel produce 300mm wafers with the same equipment but the chemistry, methodology and levers they pull to achieve the scaling is quite different.

Edit: Here's an image that was already posted publicly so hopefully I won't get into trouble. It illustrates what I mean by how different the TSMC / Intel nodes are and what they focus on. The chart on the left represents highest cell density available with a node, the one on the right represents highest performing library (i.e. HP cell performance). The leading process is represented as having a value of '1.0'.

 

[SpudLobby]

I don't know enough about the progress of 20A/18A to dispute any of this. I'm skeptical that 20A ARL is being cancelled since it'd absolutely have catastrophic consequences, although I don't take it as a given that 20A/18A will release by EOY 2024. We'll just have to wait and see.

I do know that both Intel 4 and 3 are healthy because I know people working on projects that are going to be fabricated on that process. It's possible that they fumbled 20A/18A since these are different teams working on these projects. The backup plan was Intel 4 /3 with PowerVia, I would personally look for that being productized through the fabs as a leading edge indicator that RibbonFet / GAAFet nodes are in trouble.

Yeah this is fair enough.


FWIW, I wish they’d just use Intel 3 for Arrow Lake mobile. People act like that’s something abominable and behind but it’ll have obvious enhancements in the way of density (HD libraries) and perf/W per Intel. Still fairly bullish about it.

 

[Geddagod]

As far as I know, ARL was always destined for the node that came after Intel 4 (it was called 7nm back then). Both MTL & ARL are 'de-risk' products meant to be used as a stepping stone for new process technology coupled with external process nodes. MTL at one point was intended to be a bigger deal than what we ended up receiving. Frankly, if you go back 2 years a lot of product road maps are unrecognizable to what we have today.

I think a lot of people overthink Intel’s use of TSMC processes. There’s a combination of factors involved - existing commitments, volume for cutting edge processes and cost. TSMC’s nodes also happen to be quite good in areas that Intel’s processes sometimes have issues with. Both TSMC and Intel produce 300mm wafers with the same equipment but the chemistry, methodology and levers they pull to achieve the scaling is quite different.

Edit: Here's an image that was already posted publicly so hopefully I won't get into trouble. It illustrates what I mean by how different the TSMC / Intel nodes are and what they focus on. The chart on the left represents highest cell density available with a node, the one on the right represents highest performing library (i.e. HP cell performance). The leading process is represented as having a value of '1.0'.

View attachment 83070

That's a really interesting chart. I have a lot of respect for tech insights, so I could be wrong. However when the chart mentions using the highest cell density available with the node, I have to wonder what fin counts they have i3 on vs 3E. For N3 to be 2x as dense as Intel 3... the fin count has to be different. And while techinsights appears to have the tools available to analyze existing processors on a very deep level, I wonder how they calculated performance as well. Last time what they did is use 10SF as a TSMC 7nm equivalent in perf, and scaled from there, which I think is not very accurate, or at least not very relevant for the power levels the equivalent perf was at.

 

[SpudLobby]

That's a really interesting chart. I have a lot of respect for tech insights, so I could be wrong. However when the chart mentions using the highest cell density available with the node, I have to wonder what fin counts they have i3 on vs 3E. For N3 to be 2x as dense as Intel 3... the fin count has to be different. And while techinsights appears to have the tools available to analyze existing processors on a very deep level, I wonder how they calculated performance as well. Last time what they did is use 10SF as a TSMC 7nm equivalent in perf, and scaled from there, which I think is not very accurate, or at least not very relevant for the power levels the equivalent perf was at.

I wouldn’t pay too much attention to the performance parts here without at least one consistent unit of measurement between them (a core in particular). I do think they’re probably right though that 18A with GAAFETs and in ideal yields is going to perform a good bit better than N3E.

 

[H433x0n]

That's a really interesting chart. I have a lot of respect for tech insights, so I could be wrong. However when the chart mentions using the highest cell density available with the node, I have to wonder what fin counts they have i3 on vs 3E. For N3 to be 2x as dense as Intel 3... the fin count has to be different. And while techinsights appears to have the tools available to analyze existing processors on a very deep level, I wonder how they calculated performance as well. Last time what they did is use 10SF as a TSMC 7nm equivalent in perf, and scaled from there, which I think is not very accurate, or at least not very relevant for the power levels the equivalent perf was at.

The fin configuration is without a doubt different. My impression is that they're using the N3 2-1 Fin for the density metric. Think about it in the context of the chart on the left represents the best available HD cell library, while the chart on the right represents the best available HP cells.

There's some context missing in that BPD offers benefits that aren't apparent in this chart as well.

 

[uzzi38]

@Geddagod I have very bad news for you as to what ARL-U is, if you're hoping for the possibility that ARL-U is still on 20A (and thus we'll get something there on consumer platforms).

I hope that there's a 20A consumer-aimed tile still out there that isn't canned, but my hope to that end is dwindling.

 

[Exist50]

Edit: Here's an image that was already posted publicly so hopefully I won't get into trouble. It illustrates what I mean by how different the TSMC / Intel nodes are and what they focus on. The chart on the left represents highest cell density available with a node, the one on the right represents highest performing library (i.e. HP cell performance). The leading process is represented as having a value of '1.0'.

Those charts are garbage. They're likely just doing some sort of highly naive extrapolation. If Intel 3 was competitive with N3, Intel would be using it instead.

 

[Exist50]

@Geddagod I have very bad news for you as to what ARL-U is, if you're hoping for the possibility that ARL-U is still on 20A (and thus we'll get something there on consumer platforms).

I hope that there's a 20A consumer-aimed tile still out there that isn't canned, but my hope to that end is dwindling.

Thankfully, while you're certainly right about "ARL"-U, that has no bearing on the 20A die either way.

 

[H433x0n]

Those charts are garbage. They're likely just doing some sort of highly naive extrapolation. If Intel 3 was competitive with N3, Intel would be using it instead.

We have a totally different perspective since I don’t think these charts make Intel 3 look great. I think the charts could be interpreted as bullish for HPC and internal Intel usage but will make it difficult to attract LP SoC customers.

 

[SpudLobby]

Thankfully, while you're certainly right about "ARL"-U, that has no bearing on the 20A die either way.

Why do you think he's certainly right about ARL-U and 20A? I buy the N3 rumors personally even though it sucks, I am just curious what you mean and which tiles or products you suspect might end up on 20A within the ARL product lineup.

 

[SpudLobby]

davidbepo (@davidbepo@mastodon.social)

aside from losing well, WELL over 20% in perf this also means ARL gets a node downgrade compared to MTL, its predecessor, which already failed to reach 5 GHz, ARL should regress clocks even further and while i expect IPC here to be better than AMD the massive clock gap and SMT L should mean Zen5...

mastodon.social

Oh man, I figured he would be and sure enough. Bepo is having a meltdown lmao.

 

[SpudLobby]

davidbepo (@davidbepo@mastodon.social)

all in all this means everything CPU intel will launch till AT LEAST late 25 is retarded shit, i expect and hope this will cost them dearly economically, and hope they will exit CPU development entirely and focus on nodes which as i said above seem to be good, so good retardation doesnt allow...

mastodon.social

Oh my god lol

 

[Exist50]

Why do you think he's certainly right about ARL-U and 20A? I buy the N3 rumors personally even though it sucks, I am just curious what you mean and which tiles or products you suspect might end up on 20A within the ARL product lineup.

I have my own reasons to believe his impression about ARL-U is justified, but not the ARL 20A part. Lord help me for saying this, but I think MLID might actually have this single detail correct, and they just moved the die to a lower tier ARL-S. When exactly that would arrive is a huge question, but they need a proof point before PTL hits.

 

[SpudLobby]

I have my own reasons to believe his impression about ARL-U is justified, but not the ARL 20A part. Lord help me for saying this, but I think MLID might actually have this single detail correct, and they just moved the die to a lower tier ARL-S. When exactly that would arrive is a huge question, but they need a proof point before PTL hits.

Agreed on proof, but S implies desktop? Would be an interesting choice given frequency concerns initially and I suppose primarily about low volume they could ship.


So MLID (lol) is saying this too?


Still extremely disappointing honestly, would literally have rather seen them do ARL on i3 and actually ship a load of volume, but oh well.

 

[Exist50]

Agreed on proof, but S implies desktop? Would be an interesting choice given frequency concerns initially and I suppose primarily about low volume they could ship.


So MLID (lol) is saying this too?


Still extremely disappointing honestly, would literally have rather seen them do ARL on i3 and actually ship a load of volume, but oh well.

Yes, S would imply desktop. I don't think there'd be any real frequency concerns there. Especially since it wouldn't be in the higher end chips, and it would be replacing ADL silicon anyway.

Desktop would still be quite high volume, but it all depends on timing, especially around Panther Lake.