Discussion Intel current and future Lakes & Rapids thread

[Edrick]

What are the chances you guys think Granite Rapids uses Lion Cove on Intel 3? At this point in time at least.
I think it's either that, or slightly tweaked Redwood Cove. If Redwood Cove+ is really as big of an improvement as a new core, then why not just use Lion Cove?
This is probably the most interesting debate for Intel leaks in recent times IMO haha

Lion Cove on 18A is slated for Diamond Rapids. That is the Gen where I think Intel can catch AMD.

 

[Exist50]

You don't think the mesh is a square?
I mean if the silicon between the 24X UPI and the top left corner core is 'dead silicon' I suppose you could increase the vertical space between them a bit and maybe cram a core in there to reach 16 per tile...
But that's all I got in guesses haha

Do you see what I mean about thinking outside the box now?

 

[jpiniero]

Sierra Forest starts at 144 E-cores, for now... A far cry from what the rumors said it would theoretically top out at.

I bet physically it has 160 (40x4) but 144 (36x4) is the max they are going to try to sell. Be interesting to see at what core counts they would actually be able to sell.

 

[Geddagod]

Sierra Forest starts at 144 E-cores, for now... A far cry from what the rumors said it would theoretically top out at.

MLID*
He later recanted though, I honestly think he had access to that Yuki slide a bit earlier than the rest of us, and seeing that he had to create a new video saying that SPR AP was cancelled.
Also just want to add, SPR AP being cancelled was also leaked a while back before MLID posted that vid, IIRC by retiredengineer on twitter.
Also it's one compute tile, so IG it makes sense.

 

[Geddagod]

Do you see what I mean about thinking outside the box now?

Oh ye haha.
It was still fun doing the calculations and speculating, even if in hindsight it was a giant waste of time LOL
About EMR being 2 giant compute tiles, idk if I should be very impressed or horrified

 

[Geddagod]

Lion Cove on 18A is slated for Diamond Rapids. That is the Gen where I think Intel can catch AMD.

I don't think Intel confirmed this yet, Diamond Rapids on Intel 18A.
They did confirm Clearwater Forest on Intel 18A though.
Idk if we should be worried that Intel didn't announced Diamond Rapids for 2025 like they did Clear Water forest though haha.

 

[Exist50]

Remember that Huge Raptor Cove Die? Well thats one half of the two die per Package Emerald Rapids.

View attachment 78793

Nah, it seems like it was just a mislabeled SPR MCC wafer. See, it matches exactly, even in core count. SPR MCC:

I think EMR is a 5x7 core grid. So theoretically 35c per die. But it looks like we'll never see anything >64c in a product.

 

[Saylick]

I bet physically it has 160 (40x4) but 144 (36x4) is the max they are going to try to sell. Be interesting to see at what core counts they would actually be able to sell.

Makes sense, which explains why the old slides showed a single compute tile. How prudent of them to start small then work their way up.

 

[Exist50]

I bet physically it has 160 (40x4) but 144 (36x4) is the max they are going to try to sell. Be interesting to see at what core counts they would actually be able to sell.

Yeah, that works out to quite an aggressive ramp. They need to go from a what? 80mm2? on Intel 4 to (very rough ballpark estimate) 400-500mm2 on Intel 3 in half a year. The optimist in me thinks they must have data to back up that confidence, but time will tell. If they can actually pull it off, however, it might not get them entirely out of the woods, but it would be an encouraging first step.

 

[Exist50]

Sierra Forest starts at 144 E-cores, for now... A far cry from what the rumors said it would theoretically top out at.

In theory, they could probably use two of those dies, disable the spare memory controllers, and have a 288c "SRF-AP" product. Wasn't something like that rumored at one point? If nothing else, such a product wouldn't require any new silicon, and it might be a good way to harvest SRF dies with a bad memory controller. Very curious how that all shakes out.

 

[nicalandia]

Nah, it seems like it was just a mislabeled SPR MCC wafer. See, it matches exactly, even in core count. SPR

The size and shape matches exactly, How big is that 35 core SPR Monolithic Die? It has to be around 770 mm^2. I am sure we will see Die shots soon enough

 

[Geddagod]

The size and shape matches exactly, How big is that 35 core SPR Monolithic Die? It has to be around 770 mm^2. I am sure we will see Die shots soon enough

I think they will be able to shave off a bit of area from not having to include EMIB connectors on the bottom of the die, but ye idk about die size either. Crossing fingers for die shots soon.

 

[nicalandia]

I think they will be able to shave off a bit of area from not having to include EMIB connectors on the bottom of the die, but ye idk about die size either. Crossing fingers for die shots soon.

I didn't think they would do away with the 4 tile approach in Emerald Rapids since the core count is not that much(60 vs 64), but looking at the lack luster performance I see why they are doing that even if yields are lower

 

[jpiniero]

Yeah, that works out to quite an aggressive ramp. They need to go from a what? 80mm2? on Intel 4 to (very rough ballpark estimate) 400-500mm2 on Intel 3 in half a year. The optimist in me thinks they must have data to back up that confidence, but time will tell. If they can actually pull it off, however, it might not get them entirely out of the woods, but it would be an encouraging first step.

I think it's more that the die should be very salvageable and what they get is what they get.

 

[Exist50]

The size and shape matches exactly, How big is that 35 core SPR Monolithic Die? It has to be around 770 mm^2. I am sure we will see Die shots soon enough

SPR MCC doesn't have any EMIB, but does have the full IO, so EMR will almost certainly use an adjusted core layout. Die sizes and even shapes may end up being similar, but that can't be reuse. Also, the SPR die is native 34c, but I expect EMR to get one more core. Will see if that holds true.

I didn't think they would do away with the 4 tile approach in Emerald Rapids since the core count is not that much(60 vs 64), but looking at the lack luster performance I see why they are doing that even if yields are lower

EMIB has a pretty big area (and presumably power) overhead on SPR. If yields support it, makes sense to condense the dies. Is someone is bored, they could probably do the math on cores per wafer. Not to mention rumors about cache increases.

 

[Geddagod]

About LNC
Would increasing the dispatch to ROB width from 6 to 8 be good uplift in IPC, along with the massive ROB rumors, or do you think it's BS?
I think it could make sense considering Intel's L3 is likely to continue to have terrible latency because of the inherent way they are doing chiplets, so with a giant ROB you can cover much of the latency...
But it also seems like such a waste that you have to increase core size so much just because your cache subsystem is so slow due to the way you are doing chiplets

 

[nicalandia]

If someone is bored, they could probably do the math on cores per wafer. Not to mention rumors about cache increases.

Being Optimistic here, Intel can harvest 148 fully printed dies per wafer on SPR-SP, 15 cores per die is about 2220 Cores per Wafer.


On Emerald Rapids the math is: 68 fully printed dies and 34 cores per die is 2318 cores per 300 mm wafer.


That's only 4% Higher cores printed in favor of the two large die per CPU Aproach, which is insignificant but yields should be Higher on the smaller dies as defects become a mayor issue the larger the printed die is

 

[Exist50]

Being Optimistic here, Intel can harvest 148 fully printed dies per wafer on SPR-SP, 15 cores per die is about 2220 Cores per Wafer.
View attachment 78803

On Emerald Rapids the math is: 68 fully printed dies and 32 cores per die is 2176 cores per 300 mm wafer.
View attachment 78804

That's only 2% Higher cores printed in favor of the 4 tile approach, which is insignificant but yields should be Higher on the smaller dies as defects become a mayor issue the larger the printed die is

Btw, where did you get that image from? Can't say I've seen it linked yet.

 

[nicalandia]

Btw, where did you get that image from? Can't say I've seen it linked yet.

I just did an edit to take into account the 34 Core Die.

What image?

 

[Exist50]

I just did an edit to take into account the 34 Core Die.

What image?

Oh, are you using the SPR MCC wafer to calculate the number of EMR dies that would fit?

Anyway, if we assume 35c/die, that adds a little more, and if the L3 is truly bigger, that makes the amount of active silicon yielded higher still. But I don't think there should be much of a penalty to yields, if any. Intel doesn't seem to have any way to use SPR XCC dies with dead DDR or EMIB links, so minimizing those to total die area seems to be advantageous. And the risk of each individual core being dead should be more or less the same, normalized for area and process. The mesh seems like the biggest question mark.

 

[Exist50]

About LNC
Would increasing the dispatch to ROB width from 6 to 8 be good uplift in IPC, along with the massive ROB rumors, or do you think it's BS?
I think it could make sense considering Intel's L3 is likely to continue to have terrible latency because of the inherent way they are doing chiplets, so with a giant ROB you can cover much of the latency...
But it also seems like such a waste that you have to increase core size so much just because your cache subsystem is so slow due to the way you are doing chiplets

I think the rumors regarding those two specs are at least plausible. But how they actually translate to IPC gains, I'm decidedly less convinced on. I'm very skeptical of the 30% number I've seen thrown around. That would be substantially larger than the gain Golden Cove brought. Need something more than just bigger == better for gains like that.

 

[Geddagod]

I think the rumors regarding those two specs are at least plausible. But how they actually translate to IPC gains, I'm decidedly less convinced on. I'm very skeptical of the 30% number I've seen thrown around. That would be substantially larger than the gain Golden Cove brought. Need something more than just bigger == better for gains like that.

I don't think we are going to see more than just "bigger=better" gains until NGC. Adding new structures seems like a NGC thing.
I also agree that the 30% IPC claims are BS, I think it's going to be in the regular IPC uplift ground. Just curious on how big Lion Cove could end up being lol.
It doesn't look like Intel is taking a page out of the "lower latency caches for the win" book though.

 

[Hulk]

Excuse my ignorance, I'm not up on data center systems.

What type of company would use these top-of-the line Xeon/AMD 50+ core parts and for what type of computing load?

 

[Markfw]

Excuse my ignorance, I'm not up on data center systems.

What type of company would use these top-of-the line Xeon/AMD 50+ core parts and for what type of computing load?

I will have a shot at this, from personal experience. I supported an application that was Nationwide (US) that supported thousands of users. It was an Oracle database with (from 2002-2016) hundreds of terrabytes of data, and required servers that cost in the MILLIONS of dollars. Our first upgrade was in 2004, and it cost $4.6 million just for the server. These were "partitioned" into multiple logical servers to do "regions" independently for performance reasons.

Another example. Anandtech forums. They were run on an x86 platform, and the first upgrade was to AMD Operons somewhere around 2001-2003. No idea if the database goes back that far, but Anand was still running the show then. And I don't remember the hardware, but is was a LOT of cores, and a LOT of disk space/.

NOW you have the "cloud". Cloud providers take large servers with lots of cores, and make virtual machines of whatever size people want. I am not as expert in this area, so maybe others will comment.

 

[nicalandia]

So far this is the only shot of the Sierra Forest Wafer, Am I seeing a 6 x 4 grid(Quad Core cluster per square) or a 5 x 4 grid? Two blank squares for Memory Controller