Lion Cove on 18A is slated for Diamond Rapids. That is the Gen where I think Intel can catch AMD.What are the chances you guys think Granite Rapids uses Lion Cove on Intel 3? At this point in time at least.
I think it's either that, or slightly tweaked Redwood Cove. If Redwood Cove+ is really as big of an improvement as a new core, then why not just use Lion Cove?
This is probably the most interesting debate for Intel leaks in recent times IMO haha
Do you see what I mean about thinking outside the box now?You don't think the mesh is a square?
I mean if the silicon between the 24X UPI and the top left corner core is 'dead silicon' I suppose you could increase the vertical space between them a bit and maybe cram a core in there to reach 16 per tile...
But that's all I got in guesses haha
Sierra Forest starts at 144 E-cores, for now... A far cry from what the rumors said it would theoretically top out at.
MLID*Sierra Forest starts at 144 E-cores, for now... A far cry from what the rumors said it would theoretically top out at.
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Oh ye haha.Do you see what I mean about thinking outside the box now?![]()
I don't think Intel confirmed this yet, Diamond Rapids on Intel 18A.Lion Cove on 18A is slated for Diamond Rapids. That is the Gen where I think Intel can catch AMD.
Nah, it seems like it was just a mislabeled SPR MCC wafer. See, it matches exactly, even in core count. SPR MCC:Remember that Huge Raptor Cove Die? Well thats one half of the two die per Package Emerald Rapids.
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Makes sense, which explains why the old slides showed a single compute tile. How prudent of them to start small then work their way up.I bet physically it has 160 (40x4) but 144 (36x4) is the max they are going to try to sell. Be interesting to see at what core counts they would actually be able to sell.
Yeah, that works out to quite an aggressive ramp. They need to go from a what? 80mm2? on Intel 4 to (very rough ballpark estimate) 400-500mm2 on Intel 3 in half a year. The optimist in me thinks they must have data to back up that confidence, but time will tell. If they can actually pull it off, however, it might not get them entirely out of the woods, but it would be an encouraging first step.I bet physically it has 160 (40x4) but 144 (36x4) is the max they are going to try to sell. Be interesting to see at what core counts they would actually be able to sell.
In theory, they could probably use two of those dies, disable the spare memory controllers, and have a 288c "SRF-AP" product. Wasn't something like that rumored at one point? If nothing else, such a product wouldn't require any new silicon, and it might be a good way to harvest SRF dies with a bad memory controller. Very curious how that all shakes out.Sierra Forest starts at 144 E-cores, for now... A far cry from what the rumors said it would theoretically top out at.
The size and shape matches exactly, How big is that 35 core SPR Monolithic Die? It has to be around 770 mm^2. I am sure we will see Die shots soon enoughNah, it seems like it was just a mislabeled SPR MCC wafer. See, it matches exactly, even in core count. SPR
I think they will be able to shave off a bit of area from not having to include EMIB connectors on the bottom of the die, but ye idk about die size either. Crossing fingers for die shots soon.The size and shape matches exactly, How big is that 35 core SPR Monolithic Die? It has to be around 770 mm^2. I am sure we will see Die shots soon enough
I didn't think they would do away with the 4 tile approach in Emerald Rapids since the core count is not that much(60 vs 64), but looking at the lack luster performance I see why they are doing that even if yields are lowerI think they will be able to shave off a bit of area from not having to include EMIB connectors on the bottom of the die, but ye idk about die size either. Crossing fingers for die shots soon.
Yeah, that works out to quite an aggressive ramp. They need to go from a what? 80mm2? on Intel 4 to (very rough ballpark estimate) 400-500mm2 on Intel 3 in half a year. The optimist in me thinks they must have data to back up that confidence, but time will tell. If they can actually pull it off, however, it might not get them entirely out of the woods, but it would be an encouraging first step.
SPR MCC doesn't have any EMIB, but does have the full IO, so EMR will almost certainly use an adjusted core layout. Die sizes and even shapes may end up being similar, but that can't be reuse. Also, the SPR die is native 34c, but I expect EMR to get one more core. Will see if that holds true.The size and shape matches exactly, How big is that 35 core SPR Monolithic Die? It has to be around 770 mm^2. I am sure we will see Die shots soon enough
EMIB has a pretty big area (and presumably power) overhead on SPR. If yields support it, makes sense to condense the dies. Is someone is bored, they could probably do the math on cores per wafer. Not to mention rumors about cache increases.I didn't think they would do away with the 4 tile approach in Emerald Rapids since the core count is not that much(60 vs 64), but looking at the lack luster performance I see why they are doing that even if yields are lower
If someone is bored, they could probably do the math on cores per wafer. Not to mention rumors about cache increases.
Btw, where did you get that image from? Can't say I've seen it linked yet.Being Optimistic here, Intel can harvest 148 fully printed dies per wafer on SPR-SP, 15 cores per die is about 2220 Cores per Wafer.
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On Emerald Rapids the math is: 68 fully printed dies and 32 cores per die is 2176 cores per 300 mm wafer.
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That's only 2% Higher cores printed in favor of the 4 tile approach, which is insignificant but yields should be Higher on the smaller dies as defects become a mayor issue the larger the printed die is
I just did an edit to take into account the 34 Core Die.Btw, where did you get that image from? Can't say I've seen it linked yet.
Oh, are you using the SPR MCC wafer to calculate the number of EMR dies that would fit?I just did an edit to take into account the 34 Core Die.
What image?
I think the rumors regarding those two specs are at least plausible. But how they actually translate to IPC gains, I'm decidedly less convinced on. I'm very skeptical of the 30% number I've seen thrown around. That would be substantially larger than the gain Golden Cove brought. Need something more than just bigger == better for gains like that.About LNC
Would increasing the dispatch to ROB width from 6 to 8 be good uplift in IPC, along with the massive ROB rumors, or do you think it's BS?
I think it could make sense considering Intel's L3 is likely to continue to have terrible latency because of the inherent way they are doing chiplets, so with a giant ROB you can cover much of the latency...
But it also seems like such a waste that you have to increase core size so much just because your cache subsystem is so slow due to the way you are doing chiplets
I don't think we are going to see more than just "bigger=better" gains until NGC. Adding new structures seems like a NGC thing.I think the rumors regarding those two specs are at least plausible. But how they actually translate to IPC gains, I'm decidedly less convinced on. I'm very skeptical of the 30% number I've seen thrown around. That would be substantially larger than the gain Golden Cove brought. Need something more than just bigger == better for gains like that.
I will have a shot at this, from personal experience. I supported an application that was Nationwide (US) that supported thousands of users. It was an Oracle database with (from 2002-2016) hundreds of terrabytes of data, and required servers that cost in the MILLIONS of dollars. Our first upgrade was in 2004, and it cost $4.6 million just for the server. These were "partitioned" into multiple logical servers to do "regions" independently for performance reasons.Excuse my ignorance, I'm not up on data center systems.
What type of company would use these top-of-the line Xeon/AMD 50+ core parts and for what type of computing load?