Discussion Intel current and future Lakes & Rapids thread

[moinmoin]

Notice the lack of mention of Raptor Lake mobile there btw. It's an important detail.

Does that even exist? I thought it's all ADL rebadged as 13th gen, except for the high end DTR HX series using the one RPL desktop K die.

 

[uzzi38]

Does that even exist? I thought it's all ADL rebadged as 13th gen, except for the high end DTR HX series using the one RPL desktop K die.

It is pretty much rebadged ADL, yes.

But it also runs higher peak clocks and I believe is also more efficient due to process improvements.

 

[Timmah!]

Geekbench 5 Scores for Xeon W7 2495X. Monolithic 24C/48T CPU

View attachment 76216
View attachment 76217
View attachment 76218

Why only 40 numbers? Thats neither number of cores nor threads.
Additionally, the numbers all over place. So what is the all-core clock out of these, is it 3,8 or 3,9 or 4 or 4,1? Lets see the final product and its pricing. If its 2500 like TR 5965x, then lol.

 

[IntelUser2000]

Branch prediction improves nearly every generation doesn't it? And usually branch prediction changes don't add drastically much IPC anyway right?

On the contrary. Branch prediction is pretty much a necessity because it's one of the biggest bottlenecks to instruction level parallelism, and one of the only ways to constantly increase single thread performance. Without consistent work on branch prediction over the past 20 years, the performance we get with CPUs nowadays wouldn't be possible. Without improved branch prediction, most of the other features would be rendered null. It allows modern 6+ wide decoder setups to be usable.

Remember the reason much criticized architectures like Netburst(Pentium 4) and AMD's Bulldozer performed badly was because pipeline increase was more than what could be countered by branch predictor improvements.

It's increasing cache that's very easy to do, even though internal caches like L1 is harder than increasing L3.

Also, branch predictor enhancements require significant work, because it's actually lot of thought required rather than just increasing the size of the buffers, even though it's part of it. It is the importance in performance that any significant uarch changes accompany branch prediction improvements.

Biggest reason for Load/Store changes lies in continual work in vector performance. It benefits general purpose code but at some point it's more for wider AVX. You'll notice every time SIMD width doubles, so do L/S.

 

[nicalandia]

Why only 40 numbers? Thats neither number of cores nor threads.
Additionally, the numbers all over place. So what is the all-core clock out of these, is it 3,8 or 3,9 or 4 or 4,1? Lets see the final product and its pricing. If its 2500 like TR 5965x, then lol.

It's the amount of times The benchmark detected the Single Thread Highest Speed per core. It does not always jump on all cores but it jumped 40 times(at least delectated).


All Core boost is much lower than the recorded ST Core speed. GB5 Only reports Max core speeds and those are always ST on stock Settings

 

[Timmah!]

It's the amount of times The benchmark detected the Single Thread Highest Speed per core. It does not always jump on all cores but it jumped 40 times(at least delectated).


All Core boost is much lower than the recorded ST Core speed. GB5 Only reports Max core speeds and those are always ST on stock Settings

I am aware MT clock will be lower than ST clock, but ST clock is supposed to be 4,6/4,8. That much we know from the slides and thats not the clocks we are seeing here either.
MT clocks will be very likely around 3,8GHz, but maybe could be more, thats what i am curious about.

 

[nicalandia]

I am aware MT clock will be lower than ST clock, but ST clock is supposed to be 4,6/4,8. That much we know from the slides and thats not the clocks we are seeing here either.
MT clocks will be very likely around 3,8GHz, but maybe could be more, thats what i am curious about.

True, The ST should be about 15% Higher but MT will remain about the same

 

[JoeRambo]

It won't have good ST performance no matter what. 4 channel DDR5 => penalty in latency, L3 cache with mesh architecture penalty makes already bad situation worse. The size of said L3 cache is also anemic and can't really feed so many P cores.
This is not enthusiast, but rather specialty platform as all it has is: AVX512 combined with proper I/O options for workstation. So anyone buying these already considered 7950x ( that has AVX512 ) and decent ST/MT perf and 13900K that has even better ST performance and found both lacking.

 

[Timmah!]

True

View attachment 76232

2,5 is base frequency, i am thinking all core boost. Anyway, if it needs 225W just for 2,5GHz, then uh-oh. Not cool. Then maybe even 3,8GHz boost is expecting too much.

 

[Geddagod]

On the contrary. Branch prediction is pretty much a necessity because it's one of the biggest bottlenecks to instruction level parallelism, and one of the only ways to constantly increase single thread performance. Without consistent work on branch prediction over the past 20 years, the performance we get with CPUs nowadays wouldn't be possible. Without improved branch prediction, most of the other features would be rendered null. It allows modern 6+ wide decoder setups to be usable.

Remember the reason much criticized architectures like Netburst(Pentium 4) and AMD's Bulldozer performed badly was because pipeline increase was more than what could be countered by branch predictor improvements.

It's increasing cache that's very easy to do, even though internal caches like L1 is harder than increasing L3.

Also, branch predictor enhancements require significant work, because it's actually lot of thought required rather than just increasing the size of the buffers, even though it's part of it. It is the importance in performance that any significant uarch changes accompany branch prediction improvements.

Biggest reason for Load/Store changes lies in continual work in vector performance. It benefits general purpose code but at some point it's more for wider AVX. You'll notice every time SIMD width doubles, so do L/S.

While Intel doesn't often release IPC breakdowns of their new architectures, AMD does. And based on Zen 3 and Zen 4, branch prediction changes really didn't cause a major change in IPC compared to other changes in the architecture. And I swear Intel claims better branch prediction every gen, prob cuz they tweak it a bit every gen, didnt they claim it for RPL as well?

 

[nicalandia]

It won't have good ST performance no matter what. 4 channel DDR5 => penalty in latency, L3 cache with mesh architecture penalty makes already bad situation worse. The size of said L3 cache is also anemic and can't really feed so many P cores.

I agree, Quad Channel, Low per Core L3$(1.875 MiB Per Core) and Mesh Ring are not so great.

 

[nicalandia]

Battle of The Xeons W-X processors

Intel Xeon W7-2495X 24C/48T vs Intel Xeon W7-3175X 28C/56T




The W-3175X

Geekbench Browser

 

[Timmah!]

It won't have good ST performance no matter what. 4 channel DDR5 => penalty in latency, L3 cache with mesh architecture penalty makes already bad situation worse. The size of said L3 cache is also anemic and can't really feed so many P cores.
This is not enthusiast, but rather specialty platform as all it has is: AVX512 combined with proper I/O options for workstation. So anyone buying these already considered 7950x ( that has AVX512 ) and decent ST/MT perf and 13900K that has even better ST performance and found both lacking.

Its only funny that it will be probably 3x - 5x more expensive than either 13900k/7950x, basically only because of that I/O. Which you already pay for in motherboard price.

 

[Exist50]

Does that even exist? I thought it's all ADL rebadged as 13th gen, except for the high end DTR HX series using the one RPL desktop K die.

There appears to be a legitimately new die for Raptor Lake mobile, but without the L2 increase we see in desktop Raptor Cove. It's kinda baffling. Maybe they were pinning their hopes on getting DLVR working?

 

[BorisTheBlade82]

Intel charges too much to get into consoles.

Well, Intel was in the first XBox. And if they should need some utilisation for their Fabs - which seems quite likely ATM - then why not?
I wouldn't say that they are too expensive by definition.

Branch prediction improves nearly every generation doesn't it? And usually branch prediction changes don't add drastically much IPC anyway right?
I don't really recall any leaker talking about increased OOO buffers anywhere though.
The 'wild card' I would argue is how a potentially increased L1 instruction cache as well as potential better Load/Store impact performance. And maybe there will be some touch ups on integer execution based on how that did not shrink very well compared to the rest of the core, and GLC focused heavily on the FP side.

AMD explicitly states the IPC improvement contributors since at least Zen3. This one is for Zen 4.

As @IntelUser2000 already mentioned: In addition to direct gains the Branch predictor also acts as an enabler. And it also has a huge part in minimizing wasted processing and therefore improving efficiency.

 

[moinmoin]

Well, Intel was in the first XBox.

Production of the first Xbox was also stopped at the earliest possible time since continuing it just wasn't economical for Microsoft. Other consoles are usually produced for half an eternity even after being supplanted by their successors.

 

[nicalandia]

This week Intel released Embree 4.0 as the newest version of their open-source, high performance ray-tracing library

Embree 4.0 Is Running Well On Intel 4th Gen Xeon Scalable "Sapphire Rapids" - Phoronix

www.phoronix.com

 

[nicalandia]

This is how Genoa 9654(2S) Compares with SPR-SP 8090H(2S)

2S Genoa 9654 vs 2S Sapphire Rapids 8490H - Embree 4.0 Benchmark Comparison

 

[Hitman928]

This is how Genoa 9654(2S) Compares with SPR-SP 8090H(2S)

Genoa vs Sapphire Rapids - Embree 4.0 Benchmark.

View attachment 76248

What does the 'a' bar represent in this chart?

 

[nicalandia]

What does the 'a' bar represent in this chart?

"a" bar is 2S 9654 Genoa(there is also b,c,d but I hide them from view because they have basically the same performance). Default AVX-512, All of the rest(avx, avx2 ect) are 2S 8490H

 

[BorisTheBlade82]

Production of the first Xbox was also stopped at the earliest possible time since continuing it just wasn't economical for Microsoft. Other consoles are usually produced for half an eternity even after being supplanted by their successors.

Thanks for sharing. That indeed went unnoticed for me back then.

 

[Tigerick]

Poor Intel, keep on over promising and underdelivering. Now OEM (Dell ?) has set the deadline before moving to AMD server platform.

 

[jpiniero]

Now OEM (Dell ?) has set the deadline before moving to AMD server platform.

MLID, so take it with a very large grain of salt, but it would be something like Facebook or maybe a Telco and not Dell. Dell sells AMD servers btw.

 

[igor_kavinski]

By the way, a prediction. Next CEO after Pat Gelsinger is gonna be Raja Koduri.

 

[Geddagod]

Poor Intel, keep on over promising and underdelivering. Now OEM (Dell ?) has set the deadline before moving to AMD server platform.

You mean MLID over promising and underdelivering?
This is the reason people were disappointed in RDNA 3 not beating the 4090, despite AMD never claiming it could, and their own slides at best showed it slightly behind the 4090 instead of a tier behind. This one isn't as much on MLID though as other leakers claiming 3x performance, but still...
I also can't wait for MLID "nerfed MTL" update when he claimed they axed redwood cove IPC uplifts from 15-21% to the 5-10% I'm pretty sure it's going to be, a couple months before launch (despite that not even being possible lol).
ALSO is it weird that other leakers were claiming MTL desktop was only prob going to launch mid-low end later than mobile MONTHS before MLID? Is it weird that RPL-R has also already been leaked a couple weeks ago?