According to an article posted around here, she was tasked by Gelsinger to oversee the whole thing when the delays started piling up.
Assuming they work well together. I think Rivera's task is to ensure there is proper co-ordination within teams and between the different teams involved. Regular progress updates and making sure they are on track and solving the problems before they become too big to handle.
I commented how weird that story was at the time. She joined far too late to have any impact on SPR. Business group meetings aren't what find or fix bugs. Even for GNR, if it taped out in Q2, then we've already long passed the point where she could significantly influence its direction, and one of the worst things someone can do from a project management standpoint is late changes to the specs.
Seems pretty tenuous, tbh, unless she's actually willing to commit resources to proactively solve issues. Asking for the impossible then being shocked when it all goes up in flames is how SPR happens.
The article mentioned that the delays were the result of lack of proper testing. So she's probably making sure they test GNR right and don't repeat the SPR mistakes.
Think of it in terms of the tick tock sounds that a clock makes. Tick is the faint sound. Tock is the louder one. Intel used this analogy in reverse. They should have called it tock tick to clear up confusion but of course then people would have complained, what the heck is tock tick, it doesn't exist in the real world. It's a bad analogy blah blah.
Lack of proper testing? They laid off the pre-silicon validation team, crammed in an insane amount of scope for one gen (DDR5, PCIe 5.0, CXL, Golden Cove, AMX, chiplets, accelerators, and god knows else that didn't even make it to market), and are still acting surprised it's a dumpster fire? No, any other result would have been shocking, but not this one. "Lack of proper testing" is PR speak, because they don't dare admit how bad the reality was/is.
I've been saying this for how long now? It would actually be much better for Intel if their issues were just fab related, but reality isn't so kind.
It's a cop out. They "asked too much" because they refused to hire/fund the teams necessary to pull it off.
You mean to tell me that the solution to an enormous amount of post-silicon bugs is to actually have pre-silicon validation?!? Such keen insight is clearly why they're paying her the big bucks!
No. Not entirely, at least. Ice Lake had many of the same design/validation issues of SPR, just not quite as severe. But it still shipped on what? D? E? Worse? And that probably helped contribute to the SPR delays by pulling away the already thin validation resources to get ICL-SP to market.
IIRC, part of that delay was a late discovery requiring another metal stepping, similar to SPR. Obviously, not the only issue it had, but there really are quite a few parallels between the two.
Not too bad, except the year old 5995wx beats it, and the next series is going to be out before too long.
The 5995WX it actually Crushes it, but it's the first GB Entry so we need more samples to draw a conclusion.
It seems to have a pretty commanding MT lead vs the Threadripper, from the benchmarks I'm looking at. Which ones are you referencing?
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