Discussion Intel current and future Lakes & Rapids thread

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DrMrLordX

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B) Grasp this opportunity and do something completely new and innovative, which could result in either a “home run” or a complete disaster - High Risk/High Reward. As someone mentioned earlier in this thread, we’ve seen Intel attempt do this before with Netburst and it was a catastrophe.

Ditto for Itanium.
 

Hulk

Diamond Member
Oct 9, 1999
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Yes that’s right, he joined Intel a couple of years ago I think. He’s also the pre-eminent figure of academic research into Value Prediction.

With Royal Core, I think I’m most curious to see whether if it is a completely revolutionary idea and involves crazy new features similar to some of my earlier suggestions. Or, whether it is a more contemporary and evolutionary core. (E.G: The standard improvement of: Wider, Deeper, Smarter. Just lots more of it and restarted with a clean slate)

Essentially, if you are designing a brand new core from scratch, do you either:

A) Stick to standard conventions and just remove all the old clutter and have a fresh start with traditional methods. (Basically what AMD did with Zen)

OR

B) Grasp this opportunity and do something completely new and innovative, which could result in either a “home run” or a complete disaster - High Risk/High Reward. As someone mentioned earlier in this thread, we’ve seen Intel attempt do this before with Netburst and it was a catastrophe.

At least in the early stages of development do you think they could be pursuing both A and B until one path looks like it's leading to a better result? This could be a situation where it would be good for the person at the top, who will most likely eventually steering the ship to be a person more versed in tech first and finance second rather than the reverse.
 

Exist50

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Aug 18, 2016
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This could be a situation where it would be good for the person at the top, who will most likely eventually steering the ship to be a person more versed in tech first and finance second rather than the reverse.
If Seznec's group is the one designing Royal, that would make the chief architect Debbie Marr. Not sure if that tells us anything, however. Not familiar with Intel's org chart at that level.
 

Hulk

Diamond Member
Oct 9, 1999
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If Seznec's group is the one designing Royal, that would make the chief architect Debbie Marr. Not sure if that tells us anything, however. Not familiar with Intel's org chart at that level.

Wouldn't Pat ultimately be the one to give the final "go" on something like this after hearing from everybody?
 

Exist50

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Aug 18, 2016
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Wouldn't Pat ultimately be the one to give the final "go" on something like this after hearing from everybody?
In theory, such a decision could be designated one level down, but in this particular case, you're probably right about Pat making the final call. If nothing else, any conflict between Core and Royal would have to be resolved at the top.
 

eek2121

Platinum Member
Aug 2, 2005
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An ISA roadmap for x86 in general would be a godsend. I think the problem is that right now, Intel doesn't have a clear roadmap themselves, and kind of cobble it together as they go. AVX-512 was spearheaded by Xeon Phi, and then there's all the ML and more HPC stuff added along the way, and it seems like a great big mess at the end of the day. But beyond that, they seem to view ISA differentiation as a competitive advantage, and thus keep is secret till pretty much the last possible moment. It's kind of ironic since it gives AMD years to implement the same while the software catches up.

Would be even more helpful in reverse. Imagine how much better things would be if Intel could say, for example, "All processors released past 2025 will no longer support x87 or MMX", and actually hold to that plan. Though the ideal state would be Intel and AMD actually working together. Would better fit the reality of a world where ARM is a real competitive threat.

We need a nonprofit x86 foundation to draft standards, etc. Of course it will never happen, but…
Ditto for Itanium.

Itanic!

Intel’s most successful products are rehashes of earlier ones. The original Core product was enhanced Pentium M IIRC, which was derived from the Pentium 3. Ah those were the golden days.
 

nicalandia

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Jan 10, 2019
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Nothing wrong with that as long as it is a “lower” model.
The 1380P will likely be a Higher binned/Speed Golden Cove CPU. All the info we have so far would indicate that Intel will only be releasing one CPU SKU with Raptor Cove Core(The 13900HX), The rest are Golden Cove rebranded. Which is very strange since Raptor Cove brings much improved efficiency, but it's highly likely that DLVR will be ported to this Golden Cove+ design
 
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Geddagod

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Dec 28, 2021
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Yes that’s right, he joined Intel a couple of years ago I think. He’s also the pre-eminent figure of academic research into Value Prediction.
I think it's a nice catch, but overall I don't think it's all that too revealing in terms of potential predictions for royal cove.
For example, Intel acquired SoftMachines? I think it was called, the premiere company researching and had working prototypes of core fusion. They also released a patent a couple years back about a feature that was a potential prerequisite for core-fusion. However, Ian Cutress reported that the employees in the company eventually migrated and the project got mothballed at Intel due to potential scaling issues.
With Royal Core, I think I’m most curious to see whether if it is a completely revolutionary idea and involves crazy new features similar to some of my earlier suggestions. Or, whether it is a more contemporary and evolutionary core.
My guess is that it involves crazy new features. Cores like Lion Cove seem to be the "wider, deeper, smarter" approach, considering it is rumored to go to 8 wide through out the core with a massive OOO. This could also be why Lion Cove is being confused by some leakers to be part of "Royal Core" (MLID). Lion Cove might end up being a huge uplift, but not part of Royal Core.
 

nicalandia

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Jan 10, 2019
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If they port DLVR to it, then it's also likely that they will apply the other reported "tweaks" to Intel 7 that they are using with Alder Lake as well.
It seems like release SKU Grade CPU(All current Raptor Lake) have that feature fused(was available on early ES Samples)..
Screenshot_20221128-101955_Chrome.jpg


So if DLVR has been disabled, then the power savings are coming directly from the Core design alone.
 
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Geddagod

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Dec 28, 2021
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It seems like release SKU Grade CPU(All current Raptor Lake) have that feature fused(was available on early ES Samples)..
View attachment 71873

That's actually really interesting. Wonder why the ended up fusing it off. While it might not have been enough to beat Zen 4 in efficiency, it certainly would have been a great boost regardless. Perhaps they just wanted to make sure delays were not going to happen no matter what; this is Intel we are talking about after all haha
 

nicalandia

Diamond Member
Jan 10, 2019
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That's actually really interesting. Wonder why the ended up fusing it off. While it might not have been enough to beat Zen 4 in efficiency, it certainly would have been a great boost regardless. Perhaps they just wanted to make sure delays were not going to happen no matter what; this is Intel we are talking about after all haha
This is the actual thread where it was started:

1669653309514.png

1669653383595.png


Anyone with an Early ES(Not QS) chip that would like to run some benchmarks with Enabled/Disabled to get an Understanding on performance/efficiency with that feature to be likely available on Raptor Lake Refresh and MTL
 
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Geddagod

Golden Member
Dec 28, 2021
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This is the actual thread where it was started:

View attachment 71874

View attachment 71875


Anyone with an Early ES(Not QS) chip that would like to run some benchmarks with Enabled/Disabled to get an Understanding on performance/efficiency with that feature to be likely available on Raptor Lake Refresh and MTL
I believe QXE has a ES 13700k. Not sure if it's QS or ES though. I might just ask him on discord.
Edit: he had a 13900k ES which he gave to Fritz :c
 
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Geddagod

Golden Member
Dec 28, 2021
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Perhaps DLVR will be exposed in the possible Raptor Lake Refresh product stack?
I was doubting the potential performance gain of a Raptor Lake Refresh for desktop, however the addition of DLVR can provide a 20% gain in efficiency or 7% gain in performance. Combined with an additional 50 or 150 mhz from an updated node, and potentially larger L3 cache akin to the core supposedly used for Emerald Rapids, I could see this refresh being a nice gain in performance, similar to raptor lake performance gain in ST potentially.
 

mikk

Diamond Member
May 15, 2012
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The 1380P will likely be a Higher binned/Speed Golden Cove CPU. All the info we have so far would indicate that Intel will only be releasing one CPU SKU with Raptor Cove Core(The 13900HX), The rest are Golden Cove rebranded. Which is very strange since Raptor Cove brings much improved efficiency, but it's highly likely that DLVR will be ported to this Golden Cove+ design


The processor has few internal voltage regulation (FIVR, Digital Linear voltage regulator(DLVR) to support internal power rails, for example VCCSA in DT segment .
DLVR- Digital Linear Voltage regulator, New internal VR: It consumes lower power and works within a lower temperature range. This device is not applicable for S segment



Not applicable for S segment sounds like it will be included in the mobile version which was expected from the beginning. CPU ID from 1370p is not a copy and paste from 1280p.