Discussion Intel current and future Lakes & Rapids thread

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Exist50

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Aug 18, 2016
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@IntelUser2000 @Exist50 This slide in the MTL/ARL HotChips 34 talk is quite interesting. It points to the next disaggregated design (albeit on the server side) that the Intel teams are working towards. It’s how Falcon Shores has also been described. Clearly MTL/ARL detailed in the talk is the client disaggregated platform and Falcon Shores is the common server platform equivalent, how the future modular CPU, GPU, and xPU will be built.

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I still believe Granite Rapids (and hence Sierra Forest, since they share the same platform) are being built like this. If the server design is not moved to this methodology with GNR, it will be another 2-3 years since Intel wants to do two server releases for each platform. Diamond Rapids is supposed to follow GNR on the same platform.
I do not believe Falcon Shores, even in an all-CPU config, is converged with the main server line, or at the very least not in the GNR timeframe. My understanding is that it's being handled by Raja's org, completely separate from the main Xeon CPU team. Furthermore, my understanding is that it's a significantly later project, though how much later, I don't know. Diamond Rapids, no idea, but I'd have to assume any converged architecture would be led by Xeon, from a resource perspective if nothing else.
 

moinmoin

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Jun 1, 2017
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I do not believe Falcon Shores, even in an all-CPU config, is converged with the main server line, or at the very least not in the GNR timeframe. My understanding is that it's being handled by Raja's org, completely separate from the main Xeon CPU team. Furthermore, my understanding is that it's a significantly later project, though how much later, I don't know. Diamond Rapids, no idea, but I'd have to assume any converged architecture would be led by Xeon, from a resource perspective if nothing else.
So you are essentially saying Intel's org hierarchy is preventing an earlier convergence? That would be a predictable outcome indeed considering how segmented Intel's org appears to be.
 

dullard

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So the only reliable source(regardless how early it was) says it's a mobile feature, while everyone else arguing for desktop DLVR is likely piggybacking it on misleading and widespread information from press.
I went back to look at that VideoCardz slide. What is the new vPro feature set in Raptor Lake desktop? It didn't seem to get much coverage.
 

Exist50

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So you are essentially saying Intel's org hierarchy is preventing an earlier convergence? That would be a predictable outcome indeed considering how segmented Intel's org appears to be.
Not quite. I'm saying that if the intention was to have a converged architecture, it would not make sense to have the graphics group leading the effort. Contrast this with networking, where the main Xeon team makes a chip, and then Intel's networking group builds on it to make Xeon-D and the 5G basestation chips. That doesn't seem to be what's happening for Falcon Shores.
 

LightningZ71

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I'm curious about the total price of a 2495X and 2465X on a cost reduced 4CH board with all 64 lanes exposed. I believe that Intel has a real chance to do a lot of damage to the Threadripper market in that space.
 

nicalandia

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Jan 10, 2019
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I'm curious about the total price of a 2495X and 2465X on a cost reduced 4CH board with all 64 lanes exposed. I believe that Intel has a real chance to do a lot of damage to the Threadripper market in that space.
For performance perspective(not high end features) the 13900K/S with higher clocks Would match or beat those.
 
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ashFTW

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Sep 21, 2020
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I do not believe Falcon Shores, even in an all-CPU config, is converged with the main server line, or at the very least not in the GNR timeframe. My understanding is that it's being handled by Raja's org, completely separate from the main Xeon CPU team. Furthermore, my understanding is that it's a significantly later project, though how much later, I don't know. Diamond Rapids, no idea, but I'd have to assume any converged architecture would be led by Xeon, from a resource perspective if nothing else.
In the disaggregated chips era, even the engineering teams have to be disaggregated. Individual technologies and components/chiplets should be developed by core expert teams, and then assembled into products and ”owned” for overall product definition, testing, sales, marketing etc by the individual organizations. Architecture itself including the definitions of chiplets should be cross product and carried out by a company wide group of architects with the goals of maximum flexibility, and reuse across the entire product line while still being laser-focused on predictable time to market, and regular cadence.

Facts we know from various Intel disclosures — 1) Falcon Shores (FCS) will share some x86 socket 2) FCS will come in various configurations with a mix of CPU, GPU, and other core chiplets 3) Granite Rapids (GNR) and Sierra Forest (SRF) will share the same Brich Stream platform/socket 4) GNR, SRF, and FCS are all disaggregated in nature with distinct chiplets for CPU, GPU, I/O, memory etc.

It’s possible that the main server segment (Sandra’s org) gets the SP socket while the AP socket goes to Raja’s org. But even then, it’s paramount that these products maximize the reuse of chiplets. I/O and memory chiplets are obvious candidates but even the p-core chiplet from GNR should be reusable on FCS. GNR and SRF should be identical except for their use of p-core and e-core chiplets respectively.
 
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LightningZ71

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For performance perspective(not high end features) the 13900K/S with higher clocks Would match or beat those.
It's not entirely about performance, it's about PCIe lanes. There are use cases that need those lanes badly. As to the performance, I dare say that the W7-2495X with 24 P cores, 48 threads and 4 full DDR5 channels is going to be universally faster than the 13900KS in MT and close enough in ST situations there it won't matter. It should be faster than any of the non-WX threadrippers that have ever been produced (yes, even the 32 core Zen2 one). It also stands to reason that these Xeon-W processors will have AVX-512 enabled and should be able to put a beating on any of the previous gen Threadrippers in AVX-512 tasks.

This should be a compelling product across the stack.
 
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lightisgood

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Saylick

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From Ian's Twitter:
1670269762458.png

Those manufacturing windows are pretty wide (i.e. H1 and H2). Also to clarify, the products shown next to each Intel node are just examples of products using that node. It does not mean that those products will launch in the manufacturing window.
 

nicalandia

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From Ian's Twitter:

Those manufacturing windows are pretty wide (i.e. H1 and H2). Also to clarify, the products shown next to each Intel node are just examples of products using that node. It does not mean that those products will launch in the manufacturing window.
It's a confusing slide indeed
 

Saylick

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It's a confusing slide indeed
Oh, I think Intel knew what they were doing. They need to sooth investor confidence, so presenting the products right next to the node timeline gives the impression that the products will be ready on the same timeline, when in reality there's likely another 6 months or more between HVM readiness and mass product availability.
 

dullard

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Oh, I think Intel knew what they were doing. They need to sooth investor confidence, so presenting the products right next to the node timeline gives the impression that the products will be ready on the same timeline, when in reality there's likely another 6 months or more between HVM readiness and mass product availability.
I think people are smarter than you think. Just because something is manufacturing ready does not mean it is in high volume manufacturing (you know like the first line states). Or you could read the last line that says "Technology readiness timing does not necessarily indicate product production timing."

Here is the actual slide if anyone wanted it:
 
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mderbarimdiger

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Nov 8, 2022
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I would expect Timelines presented at IEEE to represent manufacturing dates, and we should not expect Ann Kelleher to announce MTL or GNR availability dates.
 

Exist50

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Oh, I think Intel knew what they were doing. They need to sooth investor confidence, so presenting the products right next to the node timeline gives the impression that the products will be ready on the same timeline, when in reality there's likely another 6 months or more between HVM readiness and mass product availability.
They've already said, for example, Meteor Lake is a 2023 product, Granite Rapids is 2024, etc., so I don't see how one can claim this is an attempt to mislead. It's just pairing nodes with products being made on them. I think people are overthinking things.
 
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dullard

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Saylick

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I think people are smarter than you think. Just because something is manufacturing ready does not mean it is in high volume manufacturing (you know like the first line states). Or you could read the last line that says "Technology readiness timing does not necessarily indicate product production timing."

Here is the actual slide if anyone wanted it:
Fair points, but odd how the slide in the article doesn't include the fine print:
1670278507549.png
 

dullard

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Fair points, but odd how the slide in the article doesn't include the fine print:
It is odd that the slides are made and then later the legal people put on their legalese before the presentation? How do you do your slides, let the lawyers put on the legalese and then prepare the slides later?

Seems like you are overreaching. Please come back with substance rather than bashing messaging.
 
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