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Discussion Intel current and future Lakes & Rapids thread

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Me on explaining why Sapphire Rapids-SP has been delayed due to bugs and Dr. Ian Cutress was not aware of the 12th(13th currently) Steppings Intel has gone through..

Screenshot_20220917-145506_Chrome.jpg
 
Is this the most steppings of one CPU in the history of mankind?

BTW how much does each new stepping cost? I believe the changes may be made just in a few layers of the CPU, so not all the reticles need to be updated?
 
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Kocicak said:
Is this the most steppings of one CPU in the history of mankind?

BTW how much does each new stepping cost? I believe the changes may be made just in a few layers of the CPU, so not all the reticles need to be updated?
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IIRC, Broadwell made it to F, and if you go back far enough, there might be some higher numbers from when additional steppings were faster/cheaper. But in terms of money and time spent, SPR quite possibly holds the record.

Oh, and as to your question, the letter indicates the base/transistor layer and all the metal layers were changed, while the number indicates only metal layers (which ones/ how many unknown) were changed.
 
Exist50 said:
IIRC, Broadwell made it to F, and if you go back far enough, there might be some higher numbers from when additional steppings were faster/cheaper. But in terms of money and time spent, SPR quite possibly holds the record.
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Did Broadwell make it to F before it even launched?
 
Exist50 said:
Maybe? I found this article, but it seems a little unclear about what actually happened with the E-step.
www.kitguru.net

Intel to discontinue first Core M ‘Broadwell’ chips ahead of launch - KitGuru

Intel Corp.’s Core M “Broadwell” central processing units are already late to market and will be ava
www.kitguru.net www.kitguru.net
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Ohhhh you meant the client parts! Okay I can see that. Broadwell never made it to desktop (except for the -C parts) and took awhile to make it to mobile.
 
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Kocicak said:
I believe that one layer of the CPU may require few differents masks.
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If a mask is too coarse to create a layer multiple masks are used per layer indeed. That's what's called double or quad pattering (two and four masks respectively). The simplification of going from DUV to EUV is exactly by reducing the amount of masks by no longer using that multiple pattering for printing finer details. Wikipedia goes pretty deep into this topic for a change.
 
Henry swagger said:
https://twitter.com/x/status/1571113445713653762
10nm is rumping up fast intel's laptop volume increased the lead will grow bigger with raptor lake mobile coming
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Perhaps you don't realize it (or perhaps you do) but cherry-picking data sets and coming to an absurd conclusion supported by selective memory loss only makes you look like a joke poster to anyone who isn't a brand evangelist.
 
DrMrLordX said:
Did Broadwell make it to F before it even launched?
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According to Dr. Ian Cutress Intel is past F.. And its currently on G0 and not ready to Ramp Up

Screenshot_20220919-071950_Chrome.jpg


A I am with Igor and Locuza here.

A0, A1, B0, C0, C1, C2, D0, E0, E2, E3,E4,E5. It would seem that they did not stay too much on F, so let say F0 was the only F stepping then Jumped to G0 if that is the case then Intel has gone to at least 14 Steppings on Sapphire Rapids.
 
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nicalandia said:
According to Dr. Ian Cutress Intel is past F.. And its currently on G0 and not ready to Ramp Up

View attachment 67776


A I am with Igor and Locuza here.

A0, A1, B0, C0, C1, C2, D0, E0, E2, E3,E4,E5. It would seem that they did not stay too much on F, so let say F0 was the only F stepping then Jumped to G0 if that is the case then Intel has gone to at least 14 Steppings on Sapphire Rapids.
Click to expand...
I could certainly believe 14 steppings, but that ordering seems odd. It appears that they're shipping on E5, maybe E6? So why would they then do two more full steppings so soon after? Usually companies do post-launch steppings to improve yields or bin split, but then why two? I almost wonder if there's some confusion about counting. Intel often separates the stepping letters for different dies (e.g. A0 for the first die, P0 or something for the second), but if one runs far enough over, they could be forced to skip or do something else weird. Or maybe the G0 is the smaller die that's rumored? Will certainly be interesting to see what actually makes it to market.
 
I dont know much about CPU development, but I thought that there are some simulation tools available to avoid redoing the silicone again and again.

Where does the information, that it is still not ready, come from? Would it be possible to get some intel about what is currently wrong with it?

Learning about the past problems and the process of fixing it would be most interesting to many I believe. Intel should publish some study about it to improve general knowledge of processor development.
 
Kocicak said:
I dont know much about CPU development, but I thought that there are some simulation tools available to avoid redoing the silicone again and again.
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Sure, there is RTL and gate level simulation available for design verification. However the coverage on system level typically is very low for various reasons - one is simulation speed (10^6 times slower than real-time or even less).
 
Found this, thanks to Phoronix: Brown-Neri LPC 2022.09.13 Linux Intel-Hybrid Scheduling

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Running AVX2 code on E-core suffers more than running SSE.

If I was making a game engine, I would just blacklist E-cores and call it a day. The time saved could be spent doing something better.

Maybe now we know why AVX-512 isn't on E-cores. Not only would it be more power hungry, it wouldn't also be very performant.
 
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Kocicak said:
I dont know much about CPU development, but I thought that there are some simulation tools available to avoid redoing the silicone again and again.
Click to expand...
The problem seems to be that such simulation tools for a new manufacturing process are constantly in flux, as new and new data comes in about the various characteristics of the new process.

With each new stepping, they are probably updating the simulation tools in tandem, to prevent the same bugs from appearing in future silicon.
 
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