IIRC, Broadwell made it to F, and if you go back far enough, there might be some higher numbers from when additional steppings were faster/cheaper. But in terms of money and time spent, SPR quite possibly holds the record.Is this the most steppings of one CPU in the history of mankind?
BTW how much does each new stepping cost? I believe the changes may be made just in a few layers of the CPU, so not all the reticles need to be updated?
It's quite expensive, but it's already accounted for on the design/build costs.BTW how much does each new stepping cost? I believe the changes may be made just in a few layers of the CPU, so not all the reticles need to be updated?
Well, projects usually have a planned number of steppings that are budgeted in, but in the case of something like SPR, the company just has to eat the (enormous) extra cost. That, or give up.but it's already accounted for on the design/build costs
IIRC, Broadwell made it to F, and if you go back far enough, there might be some higher numbers from when additional steppings were faster/cheaper. But in terms of money and time spent, SPR quite possibly holds the record.
Maybe? I found this article, but it seems a little unclear about what actually happened with the E-step.Did Broadwell make it to F before it even launched?
Maybe? I found this article, but it seems a little unclear about what actually happened with the E-step.
Intel to discontinue first Core M ‘Broadwell’ chips ahead of launch - KitGuru
Intel Corp.’s Core M “Broadwell” central processing units are already late to market and will be avawww.kitguru.net
That is using DUV lithography. Changing to EUV like TSMC N6 6nm has greatly reduce the mask to 5 layersWow, they said that 14 nm die required 50 different masks. I wonder what is the number for todays processors.
If a mask is too coarse to create a layer multiple masks are used per layer indeed. That's what's called double or quad pattering (two and four masks respectively). The simplification of going from DUV to EUV is exactly by reducing the amount of masks by no longer using that multiple pattering for printing finer details. Wikipedia goes pretty deep into this topic for a change.I believe that one layer of the CPU may require few differents masks.
10nm is rumping up fast intel's laptop volume increased the lead will grow bigger with raptor lake mobile coming
Laptop volume and market shareWhat "lead" are you referring too?
10nm is rumping up fast intel's laptop volume increased the lead will grow bigger with raptor lake mobile coming
According to Dr. Ian Cutress Intel is past F.. And its currently on G0 and not ready to Ramp UpDid Broadwell make it to F before it even launched?
I could certainly believe 14 steppings, but that ordering seems odd. It appears that they're shipping on E5, maybe E6? So why would they then do two more full steppings so soon after? Usually companies do post-launch steppings to improve yields or bin split, but then why two? I almost wonder if there's some confusion about counting. Intel often separates the stepping letters for different dies (e.g. A0 for the first die, P0 or something for the second), but if one runs far enough over, they could be forced to skip or do something else weird. Or maybe the G0 is the smaller die that's rumored? Will certainly be interesting to see what actually makes it to market.According to Dr. Ian Cutress Intel is past F.. And its currently on G0 and not ready to Ramp Up
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A I am with Igor and Locuza here.
A0, A1, B0, C0, C1, C2, D0, E0, E2, E3,E4,E5. It would seem that they did not stay too much on F, so let say F0 was the only F stepping then Jumped to G0 if that is the case then Intel has gone to at least 14 Steppings on Sapphire Rapids.
Probably the lead weight around Intel's ankles that's dragging them down.What "lead" are you referring too?
Dr. Ian Cutress and a few other sources close to Intel.Where does the information, that it is still not ready, come from? Would it be possible to get some intel about what is currently wrong with it?
I dont know much about CPU development, but I thought that there are some simulation tools available to avoid redoing the silicone again and again.