Discussion Intel current and future Lakes & Rapids thread

[eek2121]

If Intel 4 is, as you claim, just increased EUV on the BEOL, then Intel will be further behind than I thought.

It’s not. I have seen the numbers. Will have to find a link. Intel 4 is a bit larger than TSMC N3.

Still trying to find a better source for more specific numbers, but Intel 4’s original target was 251 MTr/mm2. An update in July from AnandTech shows they have backed off a bit, but it is still much more dense than TSMC N4 or Samsung: https://www.anandtech.com/show/1682...nm-3nm-20a-18a-packaging-foundry-emib-foveros

We will see where things land, of course.

EDIT: the table on that page should be pretty eye opening for those who wonder why Intel struggled with 10nm for so long.

 

[Exist50]

but it is still much more dense than TSMC N4 or Samsung

I would not expect that to be the case. Intel's naming it nominally based on PnP vs TSMC, not density. And they haven't given any real numbers to go off of for Intel 4. Everything we have are just estimates and extrapolation.

 

[coercitiv]

Because Intel 4 is a much easier task than Intel 's 10 nm nodes.

Intel 4 is simply adding EUV to a portion of the existing Intel 7 chip. EUV is much easier to design and optimize than pushing DUV lithography to its limits. Each manufacturing step is easier and there are fewer steps which helps increase yields. This is being done with rehired good engineers and more test runs.

Sounds great in theory until we remember what happened back in 2020.

Intel's 7nm is Broken, Company Announces Delay Until 2022, 2023

The company's 7nm-based CPU product timing is shifting approximately six months relative to prior expectations. The primary driver is the yield of Intel's 7nm process, which based on recent data, is now trending approximately twelve months behind the company's internal target.

 

[dullard]

Sounds great in theory until we remember what happened back in 2020.

Intel's 7nm is Broken, Company Announces Delay Until 2022, 2023

I say Meteor Lake chips will probably be 5 quarters away (Q2 2023) in post #14,819 and you counter with a link that says they "will not debut on the market until late 2022 or early 2023." I don't really see how your link helps your case since that basically overlaps the timeline that I stated.

 

[coercitiv]

I don't really see how your link helps your case

You don't see it because you assume I'm trying to imply a different timing for Intel 4.

My point was your claim that "Intel 4 is a much easier task" is futile considering Intel already admitted to falling 12 months behind on developing this node.

 

[dullard]

You don't see it because you assume I'm trying to imply a different timing for Intel 4.

My point was your claim that "Intel 4 is a much easier task" is futile considering Intel already admitted to falling 12 months behind on developing this node.

Still irrelevant. Intel 7 problems pushing back Intel 4 from earlier projected dates does not mean Intel 4 is harder. The discussion was whether or not Meteor Lake will be end of 2023/early 2024. Yes, there are many steps that need to be correct for Meteor Lake to be released. But, those steps (while not trivial) are easier than what Intel tried to do with Intel 7.

When going from 22 nm to 14 nm to 10 nm, Intel tried to push transistor density up about 6x with the same DUV equipment! Think about it. Now they have new manufacturing equipment intended and currently used for ~7 nm production, smaller chiplets, more prototyping time, etc. The difficulties in Intel 4 are nothing compared to what they tried (and repeatedly failed to do for years) with Intel 7.

 

[jpiniero]

Still irrelevant. 10 nm problems pushing back 7 nm from earlier projected dates does not mean 7 nm is harder.

But having to eat several hundred million on PV does.

 

[coercitiv]

Still irrelevant. Intel 7 problems pushing back Intel 4 from earlier projected dates does not mean Intel 4 is harder.

I suggest you rethink your reasoning: the 7nm node from that news piece IS the Intel 4 node. In 2020 the old naming scheme was in effect.

 

[dullard]

I suggest you rethink your reasoning: the 7nm node from that news piece IS the Intel 4 node. In 2020 the old naming scheme was in effect.

My comments are in the picture:

 

[coercitiv]

So now 7nm+ is harder than 7nm, that's about it for me, I'm out of this discussion.

 

[Exist50]

Intel 7 problems pushing back Intel 4 from earlier projected dates does not mean Intel 4 is harder.

This delay was after 10nm got decent...

And dude, there's a reason Intel 3 is supposed to be a relatively quick followup.

 

[DrMrLordX]

Intel 4 is simply using EUV on the back end of line which simplifies connection designs between transistors

Umm

It’s not. I have seen the numbers.

Thought that was the general consensus. It was supposed to be at least roughly as dense as N3?

Intel 4 will be done when it's done, just pointing out that:

1). It has already seen delays. It could easily see more delays.
2). It's low-volume. Intel is taking N3 to make up for the volume reduction.
3). Leakers are already teasing an Emerald Cove product on 10ESF/Intel 7 as a stopgap after Sapphire Rapids. This implies that Granite Rapids (a key 7nm/Intel 4 product) will not be ready for market in a timely fashion. Emerald Lake might not exist though so take it for what it's worth.

So yeah maybe we'll see Meteor Lake in Q2 or Q2 2023, but in what volume? Will it be Cannonlake all over again? Or similar? If it's lower volume than IceLake-U then that will not be a good look for Intel.

 

[ashFTW]

I believe Emerald Rapids is manly focused on Sapphire Rapids based workstation chip.

 

[IntelUser2000]

Still irrelevant. Intel 7 problems pushing back Intel 4 from earlier projected dates does not mean Intel 4 is harder.

It is harder, because they are trying to significantly shrink it from Intel 7. Every process node is harder.

EUV is not a magic bullet. It's used in certain critical parts since it has less throughput. And very soon it'll need double patterning. At least DUV machines were cheaper with high throughput. Now you need double patterning with EUV? So it merely delays the inevitable.

I wouldn't be too surprised if they recover from it, but they still need to prove they can.

So yeah maybe we'll see Meteor Lake in Q2 or Q2 2023, but in what volume? Will it be Cannonlake all over again? Or similar? If it's lower volume than IceLake-U then that will not be a good look for Intel.

If it's like Cannonlake for Intel 4, it's way beyond not looking good. It'll prove to be the end of their process division. It's how it is. You need the volume not just for earning money but that's how they learn - high volume manufacturing is very different from low volume and prototyping.

You cannot skip a process, it doesn't work. It's like saying you can run before you walk. It's not possible. Either they secretly have high enough volumes or they are wishing for a dream that's not going to be fulfilled because it'll fail.

 

[Dayman1225]

Jeff Wilcox, Director of Mac System Architecture has joined Intel as a fellow and CTO of Design Engineering Group (DEG) for Client SoC architecture

I’m pleased to share that I have started a new position as Intel Fellow… | Jeff Wilcox | 179 comments

I’m pleased to share that I have started a new position as Intel Fellow, Design Engineering Group CTO, Client SoC Architecture at Intel Corporation. I could… | 179 comments on LinkedIn

www.linkedin.com

 

[dullard]

Thought that was the general consensus. It was supposed to be at least roughly as dense as N3?

There are plenty of rumors that Intel lowered their initial density goals for Intel 4. They pushed some of that density increase to Intel 3 where they are shrinking the transistor size, area savings, etc.. At first Anandtech estimated Intel 4 at 237 transistors per um^2 (1), then 200 transistors per um^2 (2), now Loihi 2 is at 71.2 transistors per um^2 (3). I realize that it is a different chip with different transistors, but Loihi 2 is not that much more dense than Intel 7.

1). It has already seen delays. It could easily see more delays.

Yes, any product can see more delays. But, Geisinger himself said "next-gen Intel 4, 3, Intel 20A, and 18A nodes is slated to begin ahead of schedule" (4). Note: to be clear since there are multiple schedules, that schedule that they are ahead of is specifically referring to coercitiv's link in July 2020. "I am happy to share that Intel 7, Intel 4, Intel 3, Intel 20A, and Intel 18A are all on or ahead of the timelines we set out in July." (5)



(1) https://www.anandtech.com/show/16656/ibm-creates-first-2nm-chip
(2) https://www.anandtech.com/show/1682...nm-3nm-20a-18a-packaging-foundry-emib-foveros
(3) https://www.anandtech.com/show/16960/intel-loihi-2-intel-4nm-4
(4) https://www.hardwaretimes.com/intel...ds-in-q1-2022-first-trillion-transistor-chip/
(5) https://semianalysis.com/intel-bett...sting-40b-43b-a-year-and-more-with-subsidies/

 

[dullard]

It is harder, because they are trying to significantly shrink it from Intel 7. Every process node is harder.

I don't think you are taking into account all of the factors that I specified. Lifting a car by hand is hard for one person, but relatively doable for 30 people by hand, and outright easy for 1 person with the right equipment. Just stating that lifting a car is hard without regard for the other details makes your reply insincere at best.

My comment was specifically that they tried to do too much with their resources with Intel 7. Yes, Intel 4 is hard--I'm not denying that. But they have more resources, the proper materials, a practical and feasible goal, and are splitting the work between Intel 4 and Intel 3 instead of doing it in one go. The combination of all the details makes Intel 4 a more achievable goal than what Intel was doing with Intel 7. That doesn't even include the extra years that Intel has had to do this work due to Intel 7 delays.

 

[DrMrLordX]

but Loihi 2 is not that much more dense than Intel 7.

That could bring a whole different set of problems.

 

[nicalandia]

Does anyone here have info on IPC gains from Raptor Cove over Golden Cove?

 

[Dayman1225]

That could bring a whole different set of problems.

Pat G said on their last earnings call that Loihi 2 uses preproduction/early development PDKs. So that could be part of the reason why it’s less dense or many other variables. Who knows all we can do is wait.

 

[mikk]

So yeah maybe we'll see Meteor Lake in Q2 or Q2 2023, but in what volume? Will it be Cannonlake all over again? Or similar? If it's lower volume than IceLake-U then that will not be a good look for Intel.

Unlike Cannonlake they have a tile design for MTL which makes things much easier as a whole, only the compute tile needs to be from Intel 4 and they don't need a highend version if they are really hard volume/yield limited, not even a 6+8 version initially. Only one ADL-P is 6+8, the others are 4+8 and ADL-U is 2+8.

Desktop gets Arrow Lake anyways and for the higher end mobile they could use Raptor Lake-H, although I hope this is not the case and we will get a full mobile lineup. From what we have heard Intel seems really optimistic about Meteor Lake. One Intel source told MLID that Intel expects Meteor Lake and onwards to leave AMD in the dust at least in the mobile space. In his last video he said Intel is confident about their Arc roadmap and Meteor Lake is also mentioned as being better than people expected and possibly hard for AMD to compete with.

 

[DrMrLordX]

Unlike Cannonlake they have a tile design for MTL which makes things much easier as a whole, only the compute tile needs to be from Intel 4

How large do you expect the compute tiles to be, and how many different compute tiles do you expect them to tape out? Heaven help us if Meteor Lake winds up being the next Cannonlake (and Intel 4 winds up being the next "gen 1" 10nm), but do remember that Cannonlake's dual core die was only 71 mm squared. And the yields were still putrid.

 

[dullard]

How large do you expect the compute tiles to be, and how many different compute tiles do you expect them to tape out? Heaven help us if Meteor Lake winds up being the next Cannonlake (and Intel 4 winds up being the next "gen 1" 10nm), but do remember that Cannonlake's dual core die was only 71 mm squared. And the yields were still putrid.

We have a couple images of Meteor Lake, but what we don't know is if those images were of a chip with many cores (say an H-series chip), or a chip with a few cores (say a U-series chip). Thus, we couldn't decide which tile was the CPU tile. I assumed the images were of an H-series chip and came up with ~105 mm^2. Others assumed that it was a U-series chip and came up with about 41 mm^2. Basically I think we can only answer with a rough range, ~41 mm^2 to ~105 mm^2. We need more info to tell which side of the range it is on.

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Page 571 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

forums.anandtech.com

 

[IntelUser2000]

@dullard Locuza said the 41mm2 die is compute portion. Also I believe Exist50 in saying that's the 41mm2 2+8 die.

Jeff Wilcox, Director of Mac System Architecture has joined Intel as a fellow and CTO of Design Engineering Group (DEG) for Client SoC architecture

I’m pleased to share that I have started a new position as Intel Fellow… | Jeff Wilcox | 179 comments

I’m pleased to share that I have started a new position as Intel Fellow, Design Engineering Group CTO, Client SoC Architecture at Intel Corporation. I could… | 179 comments on LinkedIn

www.linkedin.com

Positive indications opposite from what happened in the Kraznich days. Back in his time Intel suffered regular brain drain. Jeff Wilcox also worked at Intel before so he won't be entirely unfamiliar with the workplace.

I don't think the main motivator is money. Pat Gelsinger being at the top of the helm is. Not so much that he alone will change things radically but better positioned than before to turn it around.

 

[Exist50]

@dullard Locuza said the 41mm2 die is compute portion. Also I believe Exist50 in saying that's the 41mm2 2+8 die.

Yes. 40-ish mm2 one is 2+8 compute. Big central one is SoC. Small one next to compute is also SoC/IO. Narrow one on the end is GPU.