Discussion Intel current and future Lakes & Rapids thread

[ashFTW]

Yes. 40-ish mm2 one is 2+8 compute. Big central one is SoC. Small one next to compute is also SoC/IO. Narrow one on the end is GPU.

MTL is using Foreros, so any idea what’s on the bottom die?

 

[Exist50]

MTL is using Foreros, so any idea what’s on the bottom die?

On that product, nothing. Passive base die.

 

[ashFTW]

On that product, nothing. Passive base die.

I doubt that. Otherwise, EMIB would have been good enough to tie the 3 chiplets together, ala SPR.

 

[Exist50]

I doubt that. Otherwise, EMIB would have been good enough to tie the 3 chiplets together, ala SPR.

Doubt if you'd like. Will be proven eventually.

But note that EMIB is, I think, 45 micron, while Foveros is 36 micron. Has an impact on ubump density and efficiency.

 

[ashFTW]

Doubt if you'd like. Will be proven eventually.

But note that EMIB is, I think, 45 micron, while Foveros is 36 micron. Has an impact on ubump density and efficiency.

Gen 2 Foveros does have higher ubump density than Gen 2 EMIB, but a passive die would be more like an “old fashioned” interposer, which doesn’t deserve to be called Foreros.

 

[Exist50]

Gen 2 Foveros does have higher ubump density than Gen 2 EMIB, but a passive die would be more like an “old fashioned” interposer, which doesn’t deserve to be called Foreros.

I don't necessarily disagree, but it is what it is. And from a product standpoint, what's the alternative? For a piece of silicon that large, on a mainstream product line, it can't afford to be anything interesting. Maybe a higher tier could have something, however.

 

[jpiniero]

I don't necessarily disagree, but it is what it is. And from a product standpoint, what's the alternative? For a piece of silicon that large, on a mainstream product line, it can't afford to be anything interesting. Maybe a higher tier could have something, however.

Still seems like a waste of 10 nm capacity if it's passive. If it was active then it would not be such a waste.

 

[dullard]

@dullard Locuza said the 41mm2 die is compute portion. Also I believe Exist50 in saying that's the 41mm2 2+8 die.

Yes. 40-ish mm2 one is 2+8 compute. Big central one is SoC. Small one next to compute is also SoC/IO. Narrow one on the end is GPU.

I don't doubt Locuza or Exist50. But both just state it as a fact without public evidence. Since I have no insiders giving me info, all I can do is go off of public evidence.

Doesn't really matter to answer DrMrLordX's question though. Suppose the 41 mm^2 tile was 2+8. Then an 8+8 tile would be about 103 mm^2. And we are back with the range being ~41 mm^2 to ~105 mm^2 for the compute tile. Note: I have no idea if Meteor Lake is going to be 8+16 in some cases. That info hasn't leaked yet as far as I know. If so, then it would be in the ~123 mm^2 range.

 

[jpiniero]

Doesn't really matter to answer DrMrLordX's question though. Suppose the 41 mm^2 tile was 2+8. Then an 8+8 tile would be about 103 mm^2. And we are back with the range being ~41 mm^2 to ~105 mm^2 for the compute tile. Note: I have no idea if Meteor Lake is going to be 8+16 in some cases. That info hasn't leaked yet as far as I know. If so, then it would be in the ~123 mm^2 range.

Package certainly didn't look like there was room for anything bigger. They could make a bigger package, sure, but if Meteor Lake is meant to be a Shareholder special like Cannonlake then there wouldn't be any other need. Be the low end U and all the M models for 13th Gen, and if quality bins outperform maybe even higher end U.

 

[DrMrLordX]

I don't doubt Locuza or Exist50. But both just state it as a fact without public evidence. Since I have no insiders giving me info, all I can do is go off of public evidence.

Doesn't really matter to answer DrMrLordX's question though. Suppose the 41 mm^2 tile was 2+8. Then an 8+8 tile would be about 103 mm^2. And we are back with the range being ~41 mm^2 to ~105 mm^2 for the compute tile. Note: I have no idea if Meteor Lake is going to be 8+16 in some cases. That info hasn't leaked yet as far as I know. If so, then it would be in the ~123 mm^2 range.

Stands to reason that the 2+8 products will hit the market first.

 

[repoman27]

There are plenty of rumors that Intel lowered their initial density goals for Intel 4. They pushed some of that density increase to Intel 3 where they are shrinking the transistor size, area savings, etc.. At first Anandtech estimated Intel 4 at 237 transistors per um^2 (1), then 200 transistors per um^2 (2), now Loihi 2 is at 71.2 transistors per um^2 (3). I realize that it is a different chip with different transistors, but Loihi 2 is not that much more dense than Intel 7.

Some background as to where those numbers came from... Intel 10nm (P1274) has a known density of 100.76 MTr/mm². During the Intel 2018 Q1 earnings call, Brian Krzanich stated that the target for 7nm (P1276) scaling was 2.4x, or roughly 240 MTr/mm². At the investor meeting in May 2019, Murthy Renduchintala presented a slide that showed a 2x scaling target for 7nm, which would put it closer to 200 MTr/mm². Nonetheless, David Schor maintained that the actual reduction would end up being closer to BK's estimate and predicted the oddly specific value of 237.18 MTr/mm².

I'm not sure how Ian arrived at the 71.2 number, because if we divide 2.3 billion transistors by 31 mm² (the numbers disclosed by Intel for Loihi 2) we get 74.19 million transistors per mm². Regardless, this is in no way directly comparable to the previous MTr/mm² numbers which are density measurements for logic based on the dimensions of two specific standard cells.

Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

An outline of Intel's process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company's recent investor meeting.

fuse.wikichip.org

https://download.intel.com/newsroom/2021/new-technologies/neuromorphic-computing-loihi-2-brief.pdf

MTr/mm² - WikiChip

MTr/mm² (mega-transistor per squared millimeter) is a transistor density unit that serves as a figure of merit in quantifying a process node. The metric makes use of a weighted system consisting of two typical standard cells found in most libraries - a very small NAND2 cell and a very large...

en.wikichip.org

We have a couple images of Meteor Lake, but what we don't know is if those images were of a chip with many cores (say an H-series chip), or a chip with a few cores (say a U-series chip). Thus, we couldn't decide which tile was the CPU tile. I assumed the images were of an H-series chip and came up with ~105 mm^2. Others assumed that it was a U-series chip and came up with about 41 mm^2. Basically I think we can only answer with a rough range, ~41 mm^2 to ~105 mm^2. We need more info to tell which side of the range it is on.

We know the diameter of the wafers is 300mm, so it's not too hard to figure out the rest. The CNET photos were of a Type 4 package (MTL-M). I did my own measurements to sanity check Locuza's numbers. They're very similar, but slightly different. I'm guessing it comes down to how we adjusted for foreshortening. Feel free to do your own calculations, but here's what I came up with:

Type4 Package size: 23 mm x 19 mm
Intel 7 FOVEROS Base Tile: 16.8 mm x 10.85 mm = 182.3 mm²
Intel 4 CPU Tile: 4.8 mm x 7.9 mm = 37.9 mm²
SoC Tile: 9.0 mm x 10.5 mm = 94.5 mm²
GPU Tile: 2.25 mm x 10.5 mm = 23.6 mm²

I wouldn't expect more than a 2+8+2 configuration for MTL-M, however that CPU tile looks more like 4+8 in wafer shots. Intel may only be planning on making two CPU tiles, 4+8 and 6+8, and simply not enabling more than 2 cores for the ULV chips (U9/U15). It probably isn't worth it to do an additional tape out to go smaller than 37.9 mm².

On that product, nothing. Passive base die.

So where did the PCH go? MTL-S may have a passive base die, because Intel needs to maintain a 2-chip platform to enforce segmentation in the motherboard market, but the PCH needs to be on package for MTL-P/M.

 

[jpiniero]

So where did the PCH go?

On the SoC tile?

MTL-S may have a passive base die, because Intel needs to maintain a 2-chip platform to enforce segmentation in the motherboard market, but the PCH needs to be on package for MTL-P/M.

There is no Meteor-S. If the desktop product after Raptor is using Foveros that doesn't really change anything since they could still include a secondary PCH even if most of the IO comes from the socket itself and they could just segment the IO from the socket by brand.

 

[Exist50]

There is no Meteor-S

Don't be so hasty.

 

[jpiniero]

Don't be so hasty.

Even if they somehow magically fixed the I4 yield in time, they aren't going to do two different desktop products with two seperate sockets in the same generation. They can do that in mobile because of BGA.

 

[repoman27]

Even if they somehow magically fixed the I4 yield in time, they aren't going to do two different desktop products with two seperate sockets in the same generation. They can do that in mobile because of BGA.

Raptor Lake-S is Q3'22, Meteor Lake-S is no earlier than Q2'23. Raptor Lake is essentially ADL-S Refresh.

 

[dullard]

We know the diameter of the wafers is 300mm, so it's not too hard to figure out the rest. The CNET photos were of a Type 4 package (MTL-M). I did my own measurements to sanity check Locuza's numbers. They're very similar, but slightly different. I'm guessing it comes down to how we adjusted for foreshortening. Feel free to do your own calculations, but here's what I came up with:

Type4 Package size: 23 mm x 19 mm
Intel 7 FOVEROS Base Tile: 16.8 mm x 10.85 mm = 182.3 mm²
Intel 4 CPU Tile: 4.8 mm x 7.9 mm = 37.9 mm²
SoC Tile: 9.0 mm x 10.5 mm = 94.5 mm²
GPU Tile: 2.25 mm x 10.5 mm = 23.6 mm²

I wouldn't expect more than a 2+8+2 configuration for MTL-M, however that CPU tile looks more like 4+8 in wafer shots. Intel may only be planning on making two CPU tiles, 4+8 and 6+8, and simply not enabling more than 2 cores for the ULV chips (U9/U15). It probably isn't worth it to do an additional tape out to go smaller than 37.9 mm².

Thank you for taking the time to do the calculations. I had done my own calculations in this thread a couple months back. My calculations were similar to yours, although your measured package size was a bit smaller than Locuza's (23 mm x 20 mm) and mine (23.3 mm x 20.7 mm). Here were my calculations: https://forums.anandtech.com/thread...-rapids-thread.2509080/page-571#post-40635289

The debate was not how big each tile is, but which tile has which function. If the SOC is in the 94+mm^2 range, then what has Intel added to it? That is significantly larger than the SOC on Alder Lake. In my post above I assumed the large tile was the CPU and Locuza states that it is the GPU.

 

[jpiniero]

Raptor Lake-S is Q3'22, Meteor Lake-S is no earlier than Q2'23. Raptor Lake is essentially ADL-S Refresh.

Same generation though, Intel's been doing that where they release the K parts in the previous year but the bulk of the desktop generation has typically been Q1/Q2.

Arrow could simply be Meteor with the CPU at TSMC and additional cores/etc.

 

[dullard]

Raptor Lake-S is Q3'22, Meteor Lake-S is no earlier than Q2'23. Raptor Lake is essentially ADL-S Refresh.

A lot of people here will not accept that Intel will do rapid releases of chips. Historically Intel has averaged about 12 months per generation. But that has a wide range (19.3 months for Comet Lake -> Rocket Lake and 7.2 months for Rocket Lake -> Alder Lake).

Alder Lake -> Raptor Lake -> Meteor Lake like that is certainly on the faster end of that range, but it is what Intel keeps claiming.

 

[repoman27]

Same generation though, Intel's been doing that where they release the K parts in the previous year but the bulk of the desktop generation has typically been Q1/Q2.

Arrow could simply be Meteor with the CPU at TSMC.

I think Intel is avoiding putting all their eggs in one basket as they go mainstream with Foveros / Intel 4. We'll have Raptor Lake as Intel 7 monolithic alongside Meteor Lake Foveros / Intel 4 in the same generation.

 

[dullard]

Same generation though, Intel's been doing that where they release the K parts in the previous year but the bulk of the desktop generation has typically been Q1/Q2.

Just for reference:

All Desktop Chips	Generation	Node	Launch Date	Months As Top Chip
Nahalem		45​	01-Nov-08​	14.19​
Westmere		32​	07-Jan-10​	12.06​
Sandy Bridge	2​	32​	09-Jan-11​	15.64​
Ivy Bridge	3​	22​	29-Apr-12​	13.11​
Haswell	4​	22​	02-Jun-13​	11.99​
Haswell Refresh	4​	22​	02-Jun-14​	11.99​
Broadwell	5​	14​	02-Jun-15​	2.10​
Sky Lake	6​	14​	05-Aug-15​	12.85​
Kaby Lake	7​	14​	30-Aug-16​	13.17​
Coffee Lake	8​	14​	05-Oct-17​	12.45​
Coffee Lake Refresh	9​	14​	19-Oct-18​	10.05​
Comet Lake	10​	14​	21-Aug-19​	19.29​
Rocket Lake	11​	14​	30-Mar-21​	7.20​
Alder Lake	12​	Intel 7	04-Nov-21​	???​

 

[IntelUser2000]

The debate was not how big each tile is, but which tile has which function. If the SOC is in the 94+mm^2 range, then what has Intel added to it? That is significantly larger than the SOC on Alder Lake. In my post above I assumed the large tile was the CPU and Locuza states that it is the GPU.

Easy. Since it's a tiled architecture they can move the Display, Memory, ThunderBolt, IPU, and the Uncore along with the PCH all on the SoC tile, and SoC is System on a Chip.

41mm2 is unusually small and for mainstream Core only possible if it consists of CPU cores.

90mm2 is also too large for 192EUs when 96EUs on Intel 7 takes up under 45mm2.

I doubt that. Otherwise, EMIB would have been good enough to tie the 3 chiplets together, ala SPR.

Actually Foveros is also an option for 2.5D.

 

[dullard]

Easy. Since it's a tiled architecture they can move the Display, Memory, ThunderBolt, IPU,, and the Uncore along with the PCH all on the SoC tile, and SoC is System on a Chip.

Using Locuza's Alder Lake measurements, all that adds up to about ~74 mm^2. Where are the other 20+ mm^2 coming from? https://www.google.com/imgres?imgurl=https://pbs.twimg.com/media/FCvyypNXEAE4UKm?format=jpg&name=4096x4096&imgrefurl=https://twitter.com/locuza_/status/1454154156801921029&tbnid=48qwZP4ABOuoRM&vet=12ahUKEwjH2Jn1n6D1AhUCBs0KHQ58BRMQMygCegUIARC7AQ..i&docid=szHi3gnHAX1YVM&w=3225&h=1752&q=alder lake die shot&safe=active&ved=2ahUKEwjH2Jn1n6D1AhUCBs0KHQ58BRMQMygCegUIARC7AQ

 

[repoman27]

Thank you for taking the time to do the calculations. I had done my own calculations in this thread a couple months back. My calculations were similar to yours, although your measured package size was a bit smaller than Locuza's (23 mm x 20 mm) and mine (23.3 mm x 20.7 mm). Here were my calculations: https://forums.anandtech.com/thread...-rapids-thread.2509080/page-571#post-40635289

The debate was not how big each tile is, but which tile has which function. If the SOC is in the 94+mm^2 range, then what has Intel added to it? That is significantly larger than the SOC on Alder Lake. In my post above I assumed the large tile was the CPU and Locuza states that it is the GPU.

I think Exist50 has it mostly right, although I question whether that tiny chip next to the CPU tile contains any active logic: https://forums.anandtech.com/thread...ure-lakes-rapids-thread.2509080/post-40670687

If you look at the Alder Lake-S or Tiger Lake-U floor plans, most of the chip is neither CPU cores nor GPU EUs—it's other stuff. The SoC tile has to contain all of that "other stuff". At best that tile will be on TSMC N4, and it contains a lot of I/O which doesn't scale as well. Furthermore, even with Foveros, there will be some area penalty resulting from disaggregation.

 

[repoman27]

Using Locuza's Alder Lake measurements, all that adds up to about ~74 mm^2. Where are the other 20+ mm^2 coming from? https://www.google.com/imgres?imgurl=https://pbs.twimg.com/media/FCvyypNXEAE4UKm?format=jpg&name=4096x4096&imgrefurl=https://twitter.com/locuza_/status/1454154156801921029&tbnid=48qwZP4ABOuoRM&vet=12ahUKEwjH2Jn1n6D1AhUCBs0KHQ58BRMQMygCegUIARC7AQ..i&docid=szHi3gnHAX1YVM&w=3225&h=1752&q=alder lake die shot&safe=active&ved=2ahUKEwjH2Jn1n6D1AhUCBs0KHQ58BRMQMygCegUIARC7AQ

Tiger Lake 4+2 LP is actually a better compare than ADL-S 8+8+1 HP in terms of SoC area measurement—ADL-S doesn't have integrated Thunderbolt/USB4 or ISP/IPU. I also believe that all of the fixed function media blocks will be on the SoC tile rather than the GPU tile, if not a full GT1 GPU.

 

[IntelUser2000]

Using Locuza's Alder Lake measurements, all that adds up to about ~74 mm^2. Where are the other 20+ mm^2 coming from?

Repoman explained it really well.

-Overhead due to tiles
-Additional features
-Discrepancy between -S and mobile parts

I also believe that all of the fixed function media blocks will be on the SoC tile rather than the GPU tile, if not a full GT1 GPU.

I am doubtful of this part. Tiled architectures will need dies to be equal in size. One will be significantly larger than the other.