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Discussion Intel current and future Lakes & Rapids thread

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Perhaps we should have a separate “Future Intel Server” thread. The talk of servers gets completely drowned out by the high volume client side postings. For me only the server/workstation side (of course there are common parts) matters for both Intel and AMD.
 
Saylick said:
CNET posted a pretty cool article where they toured Intel's Arizona fab and they nabbed a few photos of Intel's future products, including Meteorlake:
20210819-intel-arizona-fab-05.jpg

20210819-intel-arizona-fab-02.jpg

20210819-intel-arizona-fab-06.jpg

20210819-intel-arizona-fab-09.jpg
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Who is the audience for this article? I assume the technologically ignorant.

This says it all.

"Intel has lagged TSMC and Samsung overall, but it's ahead with an increasingly important technology: chip packaging that lets Intel make a single processor out of multiple chip elements, variously called tiles, chiplets or dies."
 
maddie said:
Who is the audience for this article? I assume the technologically ignorant.

This says it all.

"Intel has lagged TSMC and Samsung overall, but it's ahead with an increasingly important technology: chip packaging that lets Intel make a single processor out of multiple chip elements, variously called tiles, chiplets or dies."
Click to expand...
Yeah, it's basically a PR piece for Intel to allow them to say "Look at what we're doing! We're not behind!"
 
dullard said:
Forgive me if I'm wrong here, since I don't know much about memory chips, but aren't the HBM connections central to the chip? Meaning that the gaps have to be wide?
https://en.wikipedia.org/wiki/High_...301-DSC10363_-_ZS-retouched_(29514443756).jpg
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Please see my explanation of the “HBM gap”. I’m pretty sure that’s the answer.

Discussion - Intel current and future Lakes & Rapids thread

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ashFTW said:
Based on what? There is clear evidence it that photo. You have a better explanation for 2 EMIB chiplet patters there with a big gap?
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Well first of all, you do indeed need "pinout" for both the PHY and HBM, which explains why there are two. And the signal entering the HBM die from the middle is a perfectly adequate explanation.
 
dullard said:
That is the rub. The same tweet thread that claims Meteor Lake is mobile only claims that Meteor Lake doesn't have a socket change. Those are highly unlikely to both be true.
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Pick One. Arrow Lake is mobile only, or Meteor Lake is. Not both I don’t claim to have amazing sources, but hint: Intel is on a slightly-less-than-yearly cadence with desktop. Intel is currently following a tick tock with desktop/mobile. Big changes are mobile first.

ashFTW said:
Really like the photo of the SPR chiplets on a spool.View attachment 53047
Click to expand...
maddie said:
Who is the audience for this article? I assume the technologically ignorant.

This says it all.

"Intel has lagged TSMC and Samsung overall, but it's ahead with an increasingly important technology: chip packaging that lets Intel make a single processor out of multiple chip elements, variously called tiles, chiplets or dies."
Click to expand...
Really? I never go out of my way to defend Intel, but that particular gossip piece has less relevance than me saying @maddie has poor taste in basically everything, details at 11!

EDIT: @maddie my comment is 100% nothing to do with you. I felt bad after posting it. What I meant to say was that any article claiming to have intimate details is flawed.
jpiniero said:
From the article, those are not real Meteor chips but samples for testing the bonding process. It's possible that the shapes are legit but it's not a given.
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Given that MTL is almost 3 years out, I would hope…
Exist50 said:
The shapes are indeed legit.
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Indeed. I want to replace my butter with it.
 
Exist50 said:
Well first of all, you do indeed need "pinout" for both the PHY and HBM, which explains why there are two. And the signal entering the HBM die from the middle is a perfectly adequate explanation.
Click to expand...
I disagree. We have seen only one EMIB chiplet at the edge in all the previous Intel implementations (e.g. See Ponte Vecchio). SPR will come with different chiplet sizes; Intel says UPTO ~400mm2 Per chiplet. SPR with HBM will likely come with two different SPR tile sizes as well, or at least it’s planned as a “backup” based on what AMD does. It could also just be for Aurora. Clearly it has been planned that way. We can agree to disagree and wait for Q1/Q2 next year.
 
jpiniero said:
Problem with that is that the Big Die in the center is too big to be just the CPU or the GPU. It almost has to be both, and Intel's been saying that they were splitting them.

It looks like the UP4 package but a bit bigger.
Click to expand...

It's neither. That's the SoC die.
 
Exist50 said:
It's neither. That's the SoC die.
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If that is the SoC in the middle, then it is a massive SoC.

I very quickly measured the photo. Note: take these estimated sizes with a huge grain of salt, as I didn't bother with precise corrections due to oblique camera angles. The sizes are in the image below. I'm going to guess:
1) VPU?
2) SOC. The crudely estimated shape/size is roughly the same as Alder Lake's SOC, which would make sense if it is still on Intel 7. It probably doesn't change much.
3) CPU. This is a bit smaller in both directions than Alder Lake. Adding more E-cores roughly balances the density gain from Intel 4.
4) GPU. This is a bit more narrow and a bit longer than Alder Lake. Here is where I'm more skeptical of my chip assignments, since the area seems a bit too small in the photo, given additional GPU execution units. It would make sense though if this chip was produced at TSMC on a node smaller than Intel 7.

1637340635247.png
 
dullard said:
If that is the SoC in the middle, then it is a massive SoC.

I very quickly measured the photo. Note: take these estimated sizes with a huge grain of salt, as I didn't bother with precise corrections due to oblique camera angles. The sizes are in the image below. I'm going to guess:
1) VPU?
2) SOC. The crudely estimated shape/size is roughly the same as Alder Lake's SOC, which would make sense if it is still on Intel 7. It probably doesn't change much.
3) CPU. This is a bit smaller in both directions than Alder Lake. Adding more E-cores roughly balances the density gain from Intel 4.
4) GPU. This is a bit more narrow and a bit longer than Alder Lake. Here is where I'm more skeptical of my chip assignments, since the area seems a bit too small in the photo, given additional GPU execution units. It would make sense though if this chip was produced at TSMC on a node smaller than Intel 7.

View attachment 53074
Click to expand...


The larger die seems to be the GPU tile.

locuza calculated the die sizes here:
https://twitter.com/x/status/1461548879137198086

1637341032740.png
 
Exist50 said:
It's the SoC die, not the GPU. That's the narrow one. And the 4th one isn't VPU either.
Click to expand...
The VPU is certainly just a guess based on one rumor that could be false. But why do you think the SoC chip more than doubles in size from Alder Lake to Meteor Lake?
 
dullard said:
The VPU is certainly just a guess based on one rumor that could be false. But why do you think the SoC chip more than doubles in size from Alder Lake to Meteor Lake?
Click to expand...

Chipset features, VPU?, media?, SoC cores, worse process vs CPU/GPU dies, overhead from disaggregation, etc.

Also, that's definitely 2+8.
 
Last edited:
dullard said:
Why do you ignore the 6 core i7 desktop chips (i7 970 and i7 980) that Intel sold in 2010 and 2011 when AMD wasn't much of competition? These aren't even the Extreme Edition chips.
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Intel only had those to compete with Thuban (6-core Phenom II). Once it became clear that an "8-core" Bulldozer wasn't really offering 8C levels of performance (or barely even 4C levels in some cases) Intel relegated anything with more than four cores to HEDT. Really those just prove the point even better and demonstrate how much Intel was willing to stagnate the market during that time.
 
I thought about the big tile being SoC but Intel also said they were using Foveros. Figured they would be doing the same thing they did with Lakefield and that the SoC is the base tile.

If it is the SoC I would say it would have to have a bunch of other stuff like the L3.
 
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