Discussion Intel current and future Lakes & Rapids thread

[dullard]

That is HEDT.

I changed it to Extreme Edition to be more clear. They worked in regular motherboards capable of running any i7 chip and were not marketed as HEDT. The 980x and 990x were marketed as Extreme Edition and had double the MSRP.

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[Exist50]

Kinda curious how that would align with https://videocardz.com/newz/intel-arrow-lake-p-gpu-rumored-to-feature-320-execution-units . Is one of those leaks busted already? (edit: even though they technically don't directly contradict each other they don't make that much sense together?)

I think it's probably a significant oversimplification. It makes far more sense for the split to be high end/low end, and that better aligns with the leaks. High end ARL on the best process, low-mid end MTL for mainstream market. Likewise for desktop. ARL will certainly come out later, but where they coexist, this breakdown would make sense.

 

[jpiniero]

I think it's probably a significant oversimplification. It makes far more sense for the split to be high end/low end, and that better aligns with the leaks. High end ARL on the best process, low-mid end MTL for mainstream market. Likewise for desktop. ARL will certainly come out later, but where they coexist, this breakdown would make sense.

No I think it's more likely that Meteor simply isn't coming to desktop. Both because of the wafer supply and because of the use of Foveros.

 

[Exist50]

No I think it's more likely that Meteor simply isn't coming to desktop. Both because of the wafer supply and because of the use of Foveros.

Why do you think Arrow Lake doesn't use Foveros? And N3 wafers aren't exactly easy to get.

 

[moinmoin]

Even now it's still not entirely clear how much impact AMD is having on Intel's desktop volume

Did you miss the 14nm shortage Intel suffered (well before Covid was a thing) just after Intel voluntarily increased the mainstream core count above 4 cores? You can't tell me Intel planned in advance to have shortages.

 

[jpiniero]

Why do you think Arrow Lake doesn't use Foveros?

Didn't say that. You'd want a new socket I imagine to accommodate it, if that's what they are going to do.

 

[jpiniero]

Did you miss the 14nm shortage Intel suffered (well before Covid was a thing) just after Intel voluntarily increased the mainstream core count above 4 cores?

That's because 10 nm was supposed to shoulder the load more on mobile. Intel had a ton of 10 nm production lines setup doing nothing for months.

 

[moinmoin]

That's because 10 nm was supposed to shoulder the load more on mobile. Intel had a ton of 10 nm production lines setup doing nothing for months.

While that's true, the bigger dies necessary for more cores only exacerbated the situation and reduced Intel's desktop volume.

 

[maddie]

Did you miss the 14nm shortage Intel suffered (well before Covid was a thing) just after Intel voluntarily increased the mainstream core count above 4 cores? You can't tell me Intel planned in advance to have shortages.

The mental gymnastics are awesome.

 

[jpiniero]

The mental gymnastics are awesome.

I think what you are missing is how badly 10 nm blew their plans up.

 

[Exist50]

Didn't say that. You'd want a new socket I imagine to accommodate it, if that's what they are going to do.

They could reuse the socket, but maybe not pin compatible.

 

[dullard]

Didn't say that. You'd want a new socket I imagine to accommodate it, if that's what they are going to do.

Intel just got a new LGA1700 socket. Since Meteor Lake is the first with Foveros, wouldn't your theory be that the socket change would be at Meteor Lake? I've seen rumors that Meteor Lake will be LGA1700 and rumors of LGA1800. https://videocardz.com/newz/intel-lga18xx-socket-spotted-is-it-for-meteor-lake But then, if it is mobile only, then Meteor Lake wouldn't use either socket.

 

[maddie]

I think what you are missing is how badly 10 nm blew their plans up.

Off course it blew up, the plan was foolish. Probably pushed by individuals with only a financial and marketing mindset.

Answer this. How does an extremely dominant player improve it's share price?

Entering new fields thus increasing the TAM, and/or increasing margins on its existing products. They tried both.
Nvidia is another example. AMD will be another if they ever achieve market dominance.

Intel's plan is to use as little silicon as possible to sell as a CPU. A worthy goal in isolation. 10 nm was a way for them to continue that. It must have seemed the perfect strategy as they could offer more cores AND have a smaller die size. What was the transistor density improvement for 10nm again? 2.5X?

Their desire to squeeze more margin with 10nm needing to be so much denser than 14nm backfired. Their obsession with increasing margins at the expense of other considerations led to an unrealistic plan to advance their silicon fab tech.

 

[eek2121]

Going by that list, if true this doesn't show confidence in the "Intel 4" node. Also new designs in Lion Cove and Skymont would first appear on a competing foundry by around a year.

They don't have confidence in capacity.

10SF was used on mobile forever. Intel originally confirmed their 10nm woes were fixed earlier on. Ramping up 10+ and 10SF took quite a while. I'll bet you dollars to donuts the node itself is doing just fine. Without a bunch of those fancy EUV machines, they can only produce so much.

I'm purely speculating here, but if true, it does make a lot of sense of the rumored timelines. With Raptor Lake 4Q2022 and Arrow Lake 4Q2023, that left a measly 12 months for both Raptor Lake and Meteor Lake to be around. That was quite a short lifetime for those chips. Meaning that Intel might be doing parallel plans for backup. Meteor Lake and Arrow Lake might be two forks of similar products. If Intel 4 yield is low, or if Redwood Cove/Crestmont does not perform well, then Meteor Lake would be a niche smaller-area mobile product until Arrow Lake can take over. Alternatively if TSMC N3 (which is currently in at-risk production) struggles, then Intel has Meteor Lake available to ramp up as they get more EUV instruments.

The lack of definition about the number of E-cores in Meteor Lake is also interesting. If Intel 4 yield is low, then having only 16 E cores will be easier to produce but wouldn't be very exciting as a multithreaded desktop chip in 2023. But if yield is high, then they could go up to 24 E cores.

Essentially, is this Intel's way of preventing another delay like they had with 10 nm?

Intel is going to be moving at a ridiculous cadence until they've reclaimed performance leadership or they have no way left to move forward. Intel currently has a lot of room to breathe, Meteor Lake, funny enough, will be a pretty decent jump for them. New node, new small cores, new big cores, shoot, we may not even need desktop CPUs anymore! (I kid, of course, but laptops are going to get real interesting starting early next year and moving onward).

 

[eek2121]

Intel just got a new LGA1700 socket. Since Meteor Lake is the first with Foveros, wouldn't your theory be that the socket change would be at Meteor Lake? I've seen rumors that Meteor Lake will be LGA1700 and rumors of LGA1800. https://videocardz.com/newz/intel-lga18xx-socket-spotted-is-it-for-meteor-lake But then, if it is mobile only, then Meteor Lake wouldn't use either socket.

Arrow Lake = new socket unless Meteor Lake comes to desktop. If Meteor Lake comes to desktop, it will have a new socket.

 

[dullard]

Arrow Lake = new socket unless Meteor Lake comes to desktop. If Meteor Lake comes to desktop, it will have a new socket.

That is the rub. The same tweet thread that claims Meteor Lake is mobile only claims that Meteor Lake doesn't have a socket change. Those are highly unlikely to both be true.

 

[Thunder 57]

Why do you ignore the 6 core i7 desktop chips (i7 970 and i7 980) that Intel sold in 2010 and 2011 when AMD wasn't much of competition? These aren't even the Extreme Edition chips.

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Review: https://www.anandtech.com/show/3833/intels-core-i7-970-reviewed-slightly-more-affordable-6core/3

The fact is that duopolies don't really compel companies to innovate much more than monopolies do. You'd be correct in true competition situations. But not in a duopoly and especially not in a duopoly when the two companies can distinguish their chips with each having a strong point that wins.

Because those were HEDT CPU's. Prices on those got quite ridiculous without the competition. Once AMD entered HEDT prices dropped by many hundreds of dollars.

I changed it to Extreme Edition to be more clear. They worked in regular motherboards capable of running any i7 chip and were not marketed as HEDT. The 980x and 990x were marketed as Extreme Edition and had double the MSRP.

Intel® Core™ i7-990X Processor Extreme Edition (12M Cache, 3.46 GHz, 6.40 GT/s Intel® QPI) Product Specifications

Intel® Core™ i7-990X Processor Extreme Edition (12M Cache, 3.46 GHz, 6.40 GT/s Intel® QPI) quick reference guide including specifications, features, pricing, compatibility, design documentation, ordering codes, spec codes and more.

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Product Specifications

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They still required a different socket with triple channel memory. It doesn't matter what they were called, it matters what they cost.

Fact is there was no mainstream eight core until Zen (not gonna count BD). There were some six cores such as Phenom II and BD but BD was a disaster. Phenom II x6 was decent but nothing special compared to the competition. So in a way Zen was the first mainstream six core as well.

Intel did increase IPC over the years which was welcome, but what really sucked was their "socket switcheroo" which limited upgrades and flexibility, all to sell more of their chipsets. That is why I currently prefer AMD. I buy Intel when it makes sense (BD days) and AMD when it makes sense.

 

[Saylick]

CNET posted a pretty cool article where they toured Intel's Arizona fab and they nabbed a few photos of Intel's future products, including Meteorlake:

 

[ashFTW]

Really like the photo of the SPR chiplets on a spool.

 

[moinmoin]

Interesting to see how big the gaps between EMIB endpoints appear to be, especially those for the HBM. That's a lot of area to cut out from the substrate.

 

[ashFTW]

Interesting to see how big the gaps between EMIB endpoints appear to be, especially those for the HBM. That's a lot of area to cut out from the substrate.

What do you mean by “cut out from the substrate”? Please explain. I assume, that the photo is showing some kind of imprint to help align the chiplets on the substrate.

 

[moinmoin]

What do you mean by “cut out from the substrate”? Please explain. I assume, that the photo is showing some kind of imprint to help align the chiplets on the substrate.

EMIB sinks into the substrate, the result has to be perfectly level with the substrate surface, with the dies then being put on top. Those areas where the EMIBs are put in are not carved into the substrate yet on that photo.

 

[ashFTW]

EMIB sinks into the substrate, the result has to be perfectly level with the substrate surface, with the dies then being put on top. Those areas where the EMIBs are put in are not carved into the substrate yet on that photo.

Ok, got it.
On second thought, the “gap” is actually not a gap, but the photo is showing two different positions of the EMIB connecting SPR to HBM to accommodate two different sizes of the SPR chiplet, the larger one accommodating an additional row of cores.

 

[dullard]

EMIB sinks into the substrate, the result has to be perfectly level with the substrate surface, with the dies then being put on top. Those areas where the EMIBs are put in are not carved into the substrate yet on that photo.

I think it helps others to define the terms.

EMIB = Embedded Multi-Die Interconnect Bridge. A slit is physically cut out of the substrate and a bridge is embedded into that slit. See the grey rectangle (6) that is embedded into the substrate in the image below.

 

[ashFTW]

Another observation:

There are two “rectangles“ per HBM EMIB for the presumably XCC version of SPR chiplet. Could it be that the larger configuration supports 2 HBM stacks per XCC chiplet for a total of 16GBx8 or 128GB per chip? I know that Intel has said upto 64GB, but often Intel doesn’t disclose details at the very high end. The photo shown of the assembly with one HBM stack per chiplet could be for the HCC variant.