Discussion Intel current and future Lakes & Rapids thread

[coercitiv]

I just don't know if Meteor Lake is the start of it.

According to Intel themselves it should be the start, they briefed the press on MTL using 3 dies: compute die, SOC-LP die and GPU die.

 

[ashFTW]

According to Intel themselves it should be the start, they briefed the press on MTL using 3 dies: compute die, SOC-LP die and GPU die.

I assume that the three top die are connected via some ring/mesh interconnect, which is likely to physically be on the Foveros base die. what else is there on the base die? Mem controllers, and PCIe? Or is that part of the SOC die?

 

[Joe NYC]

I hope not, that woupd artificially cap their potential. I do beliece more IGP options are good to have. More options period.

There have been some rumors about a small iGPU in the IO Die of Zen 4 desktop CPUs, which will be 6nm. So no space will be taken from computing dies.

This would be jst to boot the computer or for office work, not really a full-fledged APU

 

[StinkyPinky]

Isn't competition grand? Intel would probably still be on hex cores if it wasn't for Ryzen. Instead it looks like we'll be getting some great new hybrid CPU that crushes it in the benchmarks if nothing else.

 

[dullard]

Isn't competition grand? Intel would probably still be on hex cores if it wasn't for Ryzen. Instead it looks like we'll be getting some great new hybrid CPU that crushes it in the benchmarks if nothing else.

Competition is good, but two companies isn't competition--it is a duopoly. And Intel had 8 cores well before Ryzen. It was just in their Extreme Edition desktops. https://ark.intel.com/content/www/u...extreme-edition-20m-cache-up-to-3-50-ghz.html

Intel has plodded along, when AMD is great and also when AMD was not great.

 

[Hulk]

Isn't competition grand? Intel would probably still be on hex cores if it wasn't for Ryzen. Instead it looks like we'll be getting some great new hybrid CPU that crushes it in the benchmarks if nothing else.

Golden Cove is a pretty standard microarchitecture improvement meaning we kind of know what to expect performance-wise, it's a wider, smarter version of it's predecessor. 8 Golden Cove cores will be faster (more throughput) than Rocket Lake. Looks like they will beat Zen 3 cores per clock as well. Since there is still quite a bit of software out there that needs strong ST performance the Coves should be quite respectable. At least until AMD ups the ante...

Now the Gracemonts are more of a mystery at this point I think. How will they perform by themselves? For those applications that scale well (linearly) to 6 or 8 cores but then start to not scale as well (like Handbrake) will those Monts actually provide all the MT compute most apps require? Meaning that for many apps that don't scale linearly with cores (like ADL) perhaps they will "match" and performance will be optimized for a given die areas.

MT benchmarks generally scale linearly, meaning 10 core performance is about 10x more than single core, or 16 core performance 16x more than 1 core. Benches like that will benefit the 5950X from a scaling point of view. Real world apps maybe not so much. But then again how "strong" are these atom based Gracemont cores?

All will be revealed soon enough.

 

[igor_kavinski]

I'm just waiting to see how many issues the community will discover in existing software due to the performance disparity between the P and E cores. Like a time critical workload starting on the E core then a context switch and core to core bandwidth consumption as the Intel Thread Director realizes it needs more power and shifts it to a P core. That will consume precious cycles and add latency. It will be funny if most BIOS provide an option to disable the E cores and almost everyone conscious about performance ends up doing that.

 

[coercitiv]

Like a time critical workload starting on the E core

This was already addressed with Lakefield, the scheduler identifies foreground tasks and attempts to schedule them on P cores. Critical workloads don't start on the E cores unless all P cores are already busy doing other critical work.

 

[Joe NYC]

This was already addressed with Lakefield, the scheduler identifies foreground tasks and attempts to schedule them on P cores. Critical workloads don't start on the E cores unless all P cores are already busy doing other critical work.

Then why did we need new version of Windows?

 

[Hulk]

More napkin math...

Cinebench 20 leaked scores.
12900K MT - 11600
12700K MT - 8975
Assume 5GHz GC all-core speed and 3.7 for GM for 12900K.
Assume 4.7GHz GC all-core speed and 3.6 for GM for 12700K.
Solving simultaneous equations allows us to isolate Golden Cove and Gracemont Scores.
I arrive at 532.7 for Gracemont and 918.3 for Golden Cove.

Using these numbers and "backing into" the published 7014 CB 20 12600K score give a computed score of 6913, or about 1.4% difference from actual value. There is some consistency here, which lends some credence to the numbers.

Accounting for clockspeeds this means Golden Cove has 28% better IPC in Cinebench 20 according to these scores and calcs.

 

[Hulk]

Then why did we need new version of Windows?

I think the Thread Director provides finer grained "smarts" than the case you presented, which I think Windows 10 can currently handle.

 

[Abwx]

I arrive at 532.7 for Gracemont

Small cores scores about 400 pts@3.7GHz in CB R20 and 1040pts in CB R23.

 

[Hulk]

Small cores scores about 400 pts@3.7GHz in CB R20 and 1040pts in CB R23.

Link?

 

[Abwx]

Link?

On my previous post.

 

[dullard]

Like a time critical workload starting on the E core then a context switch and core to core bandwidth consumption as the Intel Thread Director realizes it needs more power and shifts it to a P core. That will consume precious cycles and add latency.

All workloads start on P cores unless (A) it is a background task as already identified in old or new software, (B) new software identifies it as an E core task, or (C) all P cores are busy with higher priority tasks that are actively doing work.

Then why did we need new version of Windows?

Item (C) is why Windows 11 was needed. In the past, threads were scheduled using rules-of-thumb. That is, they were scheduled without knowing if the cores or workloads were busy or not and without knowing if the cores were hot (and needing to be thermally throttled back) or cold (and could be ramped up to turbo speeds).

 

[Hulk]

On my previous post.

I don't see it? The link I mean.

 

[Asterox]

Hm, 8000mhz with CL50 latency.

https://twitter.com/x/status/1443936502883311620

 

[dullard]

Hm, 8000mhz with CL50 latency.

So at 4000 mHz frequency, does that work out to 50/(4*10^9/s) = 12.5 ns latency?

 

[Abwx]

I don't see it? The link I mean.

Despite an efficient design, the Alder Lake E-core still packs a punch. At the same frequency, it offers the same general purpose integer performance per clock as Skylake at a fraction of the power.

Alder Lake introduces a new client SoC architecture that scales from powerful desktops to…

Author: Marcus Yam, Technology Evangelist at Intel

medium.com

FTR RKL does 453.7 pts/3.7GHz in CB R20, your 532 pts /3.7Ghz is 10% better than a Zen 3 and close to what is expected from ADL P cores .

 

[Bouowmx]

Memory controller frequency: 2000 MHz

It is possible to run Gear 1 for DDR4-4000

 

[Hulk]

Alder Lake introduces a new client SoC architecture that scales from powerful desktops to…

Author: Marcus Yam, Technology Evangelist at Intel

medium.com

FTR RKL does 453.7 pts/3.7GHz in CB R20, your 532 pts /3.7Ghz is 10% better than a Zen 3 and close to what is expected from ADL P cores .

Perhaps you are comparing single thread scores with single core scores? I'm looking at individual core scores. For example 11900K does 649 CB20 ST and 6355 MT. 6355/8=794.375 per CORE. This is a 22% increase per core over per thread due to SMT (HT).

In a similar manner I calculated 918.3 CB20 per GC core for CB20. Using ST CB20 score of 770.75 (downclock to 5.0) for GC in the 12900K shows an increase due to SMT of about 19%, which is about right.

400 points for Gracemont @3.7 would mean Golden Coves would be scoring 1050pts/core and showing SMT increase of 36%, which sounds kind of high to me.

 

[moonbogg]

DDR5 is pretty crazy. Just recently that was GPU memory. I can't help but wonder what DDR5 could mean for APUs. If DDR5 for desktop is fast enough, is there any reason that a motherboard couldn't have two sockets; one for CPU and one for GPU? Imagine an upgradeable GPU that drops into your motherboard? It has to happen. Tell me it's stupid and I'll say YOUR STUPID.

 

[Joe NYC]

DDR5 is pretty crazy. Just recently that was GPU memory. I can't help but wonder what DDR5 could mean for APUs. If DDR5 for desktop is fast enough, is there any reason that a motherboard couldn't have two sockets; one for CPU and one for GPU? Imagine an upgradeable GPU that drops into your motherboard? It has to happen. Tell me it's stupid and I'll say YOUR STUPID.

It seems that future AMD GPU will have massive caches reducing need for exotic memory bandwidth. I am not sure if it can get down to DDR5. But AMD Genoa will have 12 DDR5 channels, which is a lot of bandwidth (but at high price).

Currently, CPU has the memory controllers, and the memory on mobo is attached to the CPU. So another socket for replaceable GPU would need to either tap to the same CPU connected memory or have its own memory sockets..

 

[NTMBK]

DDR5 is pretty crazy. Just recently that was GPU memory. I can't help but wonder what DDR5 could mean for APUs. If DDR5 for desktop is fast enough, is there any reason that a motherboard couldn't have two sockets; one for CPU and one for GPU? Imagine an upgradeable GPU that drops into your motherboard? It has to happen. Tell me it's stupid and I'll say YOUR STUPID.

A fixed socket for the GPU limits you to a specific power consumption and memory bus. Either it would be insanely overbuilt overkill for typical use, or it would be woefully ill equipped to handle real gaming.

 

[geegee83]

DDR5 is pretty crazy. Just recently that was GPU memory. I can't help but wonder what DDR5 could mean for APUs. If DDR5 for desktop is fast enough, is there any reason that a motherboard couldn't have two sockets; one for CPU and one for GPU? Imagine an upgradeable GPU that drops into your motherboard? It has to happen. Tell me it's stupid and I'll say YOUR STUPID.

Never seen GPUs use DDR5.

ADL integrated graphics is probably the first GPU to ever use DDR5.