Ian believes Intel has a hard deadline of the end of next year to deliver Aurora. Which means they would have to finish both Sapphire Rapids and Ponte Vecchio by then.
... which coincidentally shows a negative 3% ST IPC scaling going from 3.9 ICL to 4.7 TGL. I thought the cache subsystem of ICL was already well known.
uzzi38
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What evidence is that? Being able to hit a high turbo frequency with brute voltage and power proves absolutely nothing about power efficiency. Then there is the issue of 15w. Where is the evidence that the performance is x% better at that throttled power instead of the one minute benchmark where the test has just enough time to finish in PL1 with unlimited power? I was there when they started to degrade the power rating definition... somewhat in response to AMD also doing the same thing, but whatever.
Anyways, like people have said time will tell, just pinky promise to call out Intel marketing again when the numbers fall flat.
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People here mentioned that the base frequency has increased by >500MHz? If I’m not wrong the base frequency must be sustained on all cores and still meet TDP. Voltage will probably have to be lower at the same freq, being such a big contributor.
ST scaling is not perfect + we are comparing best score for ICL versus pre-release score for TGL?
Anyway my point was that for proper GB5 score, memory is important in several subtests.
So they managed to patch up their woefully inconsistent low voltage transistor operation to the point it might be able to compete with AMD on power rated runs... congrats I guess.
Yes, I saw that little gem last night. However, I would not expect perfect scaling, other workloads will likely hit the chip harder.
There are numerous independent benchmark results from testing/validation including a clevo and acer laptop. There is also press coverage including an AnandTech article.
DrMrLordX
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. . . which, interestingly enough, does not necessarily bode well for Rocket Lake. It doesn't really matter if its based off Sunny or Willow, all we have to do is look at the cache.
That's the rub, isn't it? What're the yields like on 10nm now? Certainly something must have improved, which is why Intel is getting better frequency/power curves out of it (and why TigerLake is actually going to perform significantly better than IceLake, we think). Even if they're getting better transistor characteristics, there's still the question of defect rate. And how many wafers are they going to have to sacrifice to IceLake-SP and Sapphire Rapids?
Zen4 is looking like a 2022 CPU now. If ADL-P can make it out in 2021, it'll face Cezanne for awhile.
IntelUser2000
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Ideally, the 40% gain would translate into 40% gain in MT and 25% gain in ST, but based on leaks it could be that Tigerlake offers Icelake CPU core performance at half the power, or 25% performance increase in general with same power.
It's 19% in ST Integer, then there's the whole user-submitted part.
1) Fair point.
2) Some not all. We'll never get Core-iso or Process-iso comparisons. For all I know 10nm SF is better than 14nm in most curves.
It's 19% in ST Integer, then there's the whole user-submitted part.
1) Fair point.
2) Some not all. We'll never get Core-iso or Process-iso comparisons. For all I know 10nm SF is better than 14nm in most curves.
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DrMrLordX
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I don't think TigerLake will ever support DDR5. Alder Lake probably will in some incarnation.
It does have support according to Dr. Ian, but actual hardware with DDR5 modules isn't expected until later in its life, which would be sometime in June next year. I'm not planning to buy it but I just want to see this CPU flex its muscles properly with the highest bandwidth memory available.
DrMrLordX
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That's odd. Alder Lake-P should be available by then, or very close to then. If it isn't . . .
Very curious choice by Intel if they put Gracemont cores in AlderLake-S according to rumors. Does that mean the "Cove" cores are really power hungry and having only these cores in the chip would mean an astronomical TDP? Something to do maybe with the limits of Silicon manufacturing at the nanoscale? Or is it because they made certain design decisions to favor performance at the expense of so much power that having too many "Cove" cores too close together becomes prohibitive?
It's the same silicon. If it's there, why not have models with the small core enabled? Plus you can say in marketing it has 16 cores.
AMD marketing won't miss the chance of making fun of that. "We only have real cores in our CPUs!"
From where did you get 1 year? It could come early 2021....or never.
That's true. Alas, I guess that Alder Lake only supports max one chiplet each, so the alternative is only having the 8 big cores enabled.
I suppose it all depends on how fast the Gracemont cores in Alder Lake actually are.
EDIT: The cores will add performance in Multi-threaded workloads, even if they are slower. Take Zen 2 per-CCX overclocking, for example.
I'm just guessing sometime around June next year would be "later in life" for Tiger Lake. Despite DDR5's higher cost, some manufacturers could decide to include it in premium laptop designs to differentiate their offerings.
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