Discussion Intel current and future Lakes & Rapids thread

[JasonLD]

It's probably two 4+4 chiplets plus an IGP chiplet. The 125 maybe 150 W TDP at base does suggest that they might indeed backport Alder Lake to 14nm. Given when it'd be released (likely two years from now) you would think they would consider 7 nm.

Wouldn't surprise me if the 6+0 was Rocket Lake's CPU chiplet.

Going 2 CPU chiplets would defeat the purpose the using big+little in the first place. It also looks like something that makes more sense for H-series than desktop -S.

 

[vstar]

Gracemont should have IPC between SKL to Sunny Cove.
Not too shabby at all, especially if it's towards the higher end of the scale.

Wow, that would be pretty awesome indeed!

I'm pretty excited for 2021 and beyond, looks like both AMD and Intel will have some great tech coming out!

 

[coercitiv]

Going 2 CPU chiplets would defeat the purpose the using big+little in the first place.

What purpose would big+little have on desktop?

 

[jpiniero]

Seems strange on the desktop though. I would think big/little would be more suited for mobile, where you could operate on the small cores to save power until a heavy load required the big cores. I think the problem is that yields/power consumption on 10 nm is still not what it should be, so they cant make a 12 or 16 core with manageable power consumption or yields.

Since you're already spending the silicon on the little cores, may as well put it on the desktop as well?

Going 2 CPU chiplets would defeat the purpose the using big+little in the first place.

I guess it would depend on the implementation. It could be one CPU chiplet but that would mean the 8+8 would have to support all the way down to Y parts. I suppose that the 6+0 could be the cut down chiplet, and products from the entire lineup would be derived from either one.

 

[mikk]

Gracemont should have IPC between SKL to Sunny Cove.
Not too shabby at all, especially if it's towards the higher end of the scale.

With a similar IPC jump similar to Tremont I would say IPC between Haswell and Skylake...unless AVX code is used. But the question is also if the little cores can scale up to 4 Ghz or more, I mean the current little cores are low clocked.

 

[OriAr]

With a similar IPC jump similar to Tremont I would say IPC between Haswell and Skylake...unless AVX code is used. But the question is also if the little cores can scale up to 4 Ghz or more, I mean the current little cores are low clocked.

Goldmont plus has IPC between Core and Nehalem, and Tremont is 32% on top of that, so between Sandy Bridge and Haswell IPC.
Another 30% on top of that gets you between SKL and Sunny Cove.

 

[RetroZombie]

Really interested in why they chose this option and not to go with more 'BIG' cores instead.

A proper usage of those, where the OS is aware of the small cores sending the background services, background processes, schedule tasks, ex. keep the system downloading files even at suspend, and lower the idle power usage, all those things are great for desktop and mobile usage.

The bad, probably needs to remove HT support because that would end with excessive cores, weird and unbalanced performance with not aware OS and APPS of the 'big little' cores, unless they aren't all available to the OS simultaneously.

 

[JasonLD]

What purpose would big+little have on desktop?

Not much, if none at all. I don't have much faith on that rumor. Sticking 12 Big cores would make more sense than going 8+8 on desktop.

I guess it would depend on the implementation. It could be one CPU chiplet but that would mean the 8+8 would have to support all the way down to Y parts. I suppose that the 6+0 could be the cut down chiplet, and products from the entire lineup would be derived from either one.

Not necessary unless Intel suddenly wants to adopt AMD's approach on using chiplets on multiple configurations. Y parts will be entirely different thing.

 

[Markeyse]

https://videocardz.com/newz/intel-alder-lake-s-to-feature-16-cores-125-150w-tdp-and-pcie-4-0

Some new information on ADL-S. Looks like Intel is planning a heterogeneous mix of cores for the desktop (8 big + 8 small). Really interested in why they chose this option and not to go with more 'BIG' cores instead.

That is interesting, but may not be for all skus. I think something else is a play here.

Going 2 CPU chiplets would defeat the purpose the using big+little in the first place. It also looks like something that makes more sense for H-series than desktop -S.

I agree. I also think that the monolithic design for Intel is now dead. AMD proved the chiplet design gets you more for less.

Wow, that would be pretty awesome indeed!

I'm pretty excited for 2021 and beyond, looks like both AMD and Intel will have some great tech coming out!

It's gonna be very exciting!

 

[jpiniero]

Not much, if none at all. I don't have much faith on that rumor. Sticking 12 Big cores would make more sense than going 8+8 on desktop.

The base TDP suggests that power consumption is a problem. That's why I mentioned 14 nm.

 

[mikk]

The base TDP suggests that power consumption is a problem. That's why I mentioned 14 nm.

While ignoring the 8+8+1 80W variant. The little cores at a sufficient desktop clock won't be for free, there are 16 cores after all. If this is 14nm it's remarkable. Realistically if you say 14nm in this case the best bet is 10nm because you are usually wrong with all your Intel speculations. You told ADL-S is dead and it isn't, by the way didn't you tell DG2 is dead not long ago? It has been added to Intels confidential content page recently, just another example of your track record.

 

[IntelUser2000]

With a similar IPC jump similar to Tremont I would say IPC between Haswell and Skylake...unless AVX code is used. But the question is also if the little cores can scale up to 4 Ghz or more, I mean the current little cores are low clocked.

Oriar is right. It would put it on par with today's "Big" cores. They'll need it because the ARM cores are getting there.

Also, Gracemont has ST perf/Vector perf and Frequency as its goals. So 4GHz may be in the horizon.

 

[JasonLD]

The base TDP suggests that power consumption is a problem. That's why I mentioned 14 nm.

Can't really say it is a problem or not without any mention of clock speeds. If they are trying to push well beyond 4Ghz, then I would expect that TDP even in 10nm.

 

[Nothingness]

Also, Gracemont has ST perf/Vector perf

What do you call "Vector perf"?

 

[NostaSeronx]

What do you call "Vector perf"?

Could be anything:
- SIMD width increased
- Amount of SIMDs increased
- Lower latency SIMDs
- Could be 3-operand AVX

Atom's devs appear to have some Zen bois in its pool. So, could be increased SIMD count and AVX.
2012 – 2016, 4 years => Design and Implementation of next-gen AMD Zen(RYZEN), Jaguar x86 CPU Cores
2016 – Present, 4 years => Atom CPU Design and Implementation

 

[DrMrLordX]

I'm curious as to why Intel feels the need to use Gracemont cores at all on desktop parts.

 

[jpiniero]

While ignoring the 8+8+1 80W variant.

Presumably the 80 W replaces the typical 65 W model. I would expect them to reduce the base clock on the big cores rather than increase the TDP there, but they feel like they need it to be 80 I guess.

 

[NTMBK]

What purpose would big+little have on desktop?

Marketing Got to keep up with those AMD 16 core chips somehow- spamming a small, low power core to make up the number seems like an economical way to still compete while being stuck on 14nm.

 

[Gideon]

Marketing Got to keep up with those AMD 16 core chips somehow- spamming a small, low power core to make up the number seems like an economical way to still compete while being stuck on 14nm.

If it's truly a 8C (Big) + 8C (Little) chiplets, IMO intel shoud just do a desktop version with 2x the big cores

 

[uzzi38]

Oriar is right. It would put it on par with today's "Big" cores. They'll need it because the ARM cores are getting there.

Also, Gracemont has ST perf/Vector perf and Frequency as its goals. So 4GHz may be in the horizon.

Goldmont Plus caps out 2.8GHz. 4GHz is a bit of a stretch IMO. Mid 3GHz is probably a safer bet.

 

[DrMrLordX]

Marketing

It's not really a good look for them when they can't field more than 8 Golden Cove cores in a 150W TDP CPU.

edit: added "more than". Obviously they do plan on selling 8-core golden cove in 150W TDP, with some little cores to boot. But still.

 

[bullzz]

What purpose would big+little have on desktop?

y'all asked for moar cores. y'all asked for low TDP. monkey's paw.

 

[RetroZombie]

y'all asked for moar cores. y'all asked for low TDP. monkey's paw.

Yeah but where is it, and then this:

big.Little configuration will become available with an 80W or 125W TDP. According to the notes, Intel is also “investigating performance scaling up to 150W.”

Like if having higher TDP is a good thing, just LOL

 

[IntelUser2000]

What do you call "Vector perf"?

Lakefield has no ISA parity. Wikichip says AVX won't work on Core chips for Lakefield.

If Gracemont has support for AVX-512, that will change. It doesn't need full width. 2x cycles using 256-bit units or 4x cycles with 128-bit cycles will work.

 

[Richie Rich]

Goldmont plus has IPC between Core and Nehalem, and Tremont is 32% on top of that, so between Sandy Bridge and Haswell IPC.
Another 30% on top of that gets you between SKL and Sunny Cove.

Exactly, Gracemont with IPC around Sky Lake would be pretty powerfull and IMO it's not correct to be named as LITTLE core (as ARM's LITTLE cores are typically very low IPC in-order cores). It's more like MIDDLE core: saving a lot of die space and energy while delivering 80% IPC of Sunny Cove (or 60% of Golden Cove).

8x Golden Cove (IPC +40% over SKL) + 8x cores of SKL IPC .... this thing could be pretty competitive against Zen3 and Zen4.