Discussion Intel current and future Lakes & Rapids thread

[Markfw]

I think ICL is 10nm at this chart.
10+ is TGL.

well, and it came out almost at the end of 2019, so thats my point. It could be another year until we see 10+

 

[OriAr]

well, and it came out almost at the end of 2019, so thats my point. It could be another year until we see 10+

Early August is hardly the end of the year.
We will see TGL in summer 2020 I think.

 

[DrMrLordX]

I dont think the interpretations in here are correct. I think there will be 10nm desktop next year. Got some confirmation of that last night.

Non NUC

. . . really? No.

That’s true, could be a limited release to one OEM like cannondale. Maybe no customer was interested in a 26 core part.

Based on the power levels of the 38c part, it may be that nobody will be interested in that either! Of course, we don't know clockspeeds on that part. But still.

Can you give me a source or confirmation for this? From my informations I have Alder Lake-S is in the works, the next step after Rocket Lake-S.

Rocket Lake-S is a 2021 part. That would put Alder Lake-S in late 2021 or 2022, unless Intel pulls Rocket Lake-S forward.

and now the Intel machine is in high gear,.

Yay? We already knew about Comet Lake-S.

if they fake the 10nm news, that will be the end of Intel as we know it today

No it won't. They already fudged on Cannonlake and got away with it. They have delayed IceLake-SP interminably and gotten away with it. Sapphire Rapids, which originally was supposed to be a major architectural change for Intel, turned out to be mostly IceLake with different packaging, and nobody has turned on them over that either. The only thing that can end Intel is competition.

From the same article, Intel has said that yield improvement on 10nm is ahead of schedule.

I think ICL is 10nm at this chart.
10+ is TGL.

I would not be so sure about that, unless as Mark indicates that the lovely blue bars mean "availability by the end of the year, conditionally". For example, Intel can't produce 10nm anything on the desktop or server in 2019, yet they show 10nm for 2019. Because IceLake-U? Even Tremont-based products are going to be very rare this year. It's really difficult to take Intel seriously until they actually change what is available in retail channels. What I see is a lot of hype to turn people's attention away from products that can be purchased today.

 

[Ajay]

No it won't. They already fudged on Cannonlake and got away with it. They have delayed IceLake-SP interminably and gotten away with it. Sapphire Rapids, which originally was supposed to be a major architectural change for Intel, turned out to be mostly IceLake with different packaging, and nobody has turned on them over that either. The only thing that can end Intel is competition.

Where did you read that SR is basically ICL?

Competition can’t beat Intel right now because AMD (TSMC) doesn’t have the fab capacity to do so. I don’t see that changing in the next few years because ARM SoCs take the bulk of the wafers that TSMC fabs produce. Competition for wafers will be tight even with TSMC's expansion plans (Added An additional $4B US for capital investment).

 

[NostaSeronx]

Where did you read that SR is basically ICL?

Via sources unnamed.. Sapphire Rapids was converted to be the >76-core Icelake-AP part.

However, my source says it will be WillowcoveX w/ >80 cores with the MDFI. Which will be done in a die mesh, with maybe four I/O agents(w/ HBM) and 8x16 WLCx dies w/ post-UPI CHA L4.

 

[mikk]

Basically the only infos we have about Sapphire Rapids is the support of DDR5 and PCIe 5. Obviously the Icelake IMC don't support DDR5, they need more than Icelake in a different package for this change. Claiming "it turned out to be mostly Icelake in a different package" is FUD at this point.

 

[DrMrLordX]

Basically the only infos we have about Sapphire Rapids is the support of DDR5 and PCIe 5. Obviously the Icelake IMC don't support DDR5, they need more than Icelake in a different package for this change. Claiming "it turned out to be mostly Icelake in a different package" is FUD at this point.

Is it Sunny Cove or Willow Cove? It isn't a drastically new uarch regardless.

edit: okay I'm going to retract that statement since it looks like Sapphire Rapids is actually Willow Cove:

News | Latest tech news & rumours | Trusted Reviews

Read about the latest tech news and developments from our team of experts, who provide updates on the new gadgets, tech products & services on the horizon.

www.theinquirer.net

Looks like Sapphire Rapids is turning out more like Tiger Lake-SP than anything else.

 

[NostaSeronx]

Is it Sunny Cove or Willow Cove? It isn't a drastically new uarch regardless.

It is neither. It is either SunnycoveX or WillowcoveX. Client(Corename) cores are mostly-inclusive with small caches, while server(CorenameX) cores are mostly-exclusive with big caches.

The X-class cores are internally called "Super Core", even though they never choose to use that in marketing. Then, there is also TremontX, not sure if they are calling "Super Atom". I don't think they are internally calling the Server-class Atom cores, Super Atom like they did for converged core plan w/ SkylakeX/SunnycoveX/CannonlakeX(never appeared)/WillowcoveX.

 

[mikk]

Is it Sunny Cove or Willow Cove? It isn't a drastically new uarch regardless.

edit: okay I'm going to retract that statement since it looks like Sapphire Rapids is actually Willow Cove:

This is all speculative. It could be Willow Cove, it could be Golden Cove, it could be a hybrid between the two...however it surely isn't Sunny Cove because Icelake gets Sunny Cove, from where did you get this? In the worst case it is "only" Willow Cove based, and of course the server core is probably a bit different to the mainstream Willow Cove in this case. Sapphire Rapids comes with a new LGA platform with DDR5 and PCIe5.

 

[TheGiant]

It is neither. It is either SunnycoveX or WillowcoveX. Client(Corename) cores are mostly-inclusive with small caches, while server(CorenameX) cores are mostly-exclusive with big caches.

The X-class cores are internally called "Super Core", even though they never choose to use that in marketing. Then, there is also TremontX, not sure if they are calling "Super Atom". I don't think they are internally calling the Server-class Atom cores, Super Atom like they did for converged core plan w/ SkylakeX/SunnycoveX/CannonlakeX(never appeared)/WillowcoveX.

Any news of the x variants?
Is Intel working on improving gaming performance or better say latency?

 

[trivik12]

One thing is market is full of ice lake laptops. I see them more than even comet lake ones. Of course you can still buy coffee lake or whiskey lake laptop as well. Lots of deals. for BF you can buy a icelake with 12gb/512GB SSD for $480. So let us see we see shortages post these sales.

 

[NostaSeronx]

Any news of the x variants?
Is Intel working on improving gaming performance or better say latency?

The x-variants aren't going to be on the 272-nm(low power track library), but rather on mid-power/mid-perf(340-nm) to high-perf(408-nm).
Gaming isn't the concern for any of the corex models. It is all about crunching those universal-emulation simulations.

Potentially, looking at SkylakeX, at four 256-bit units that can fuse into two AVX512 for SunnycoveX. Port0/Port1 being the first AVX512 unit and Port5/6 being the second AVX512 unit.

1x full-ISA AVX512 on average for older SkylakeX/Sunnycove to 2x full-ISA AVX512 on SunnycoveX. Anything to get to full throughput across all AVX3 levels: 128b(4), 256b(4), 512b(2). Which I believe the ultra-wide WillowcoveX(&Willowcove-client) will solve.

AVX3 => Unbroken implementation. Capable of ignoring XMM, YMM, ZMM designations, basically VMM0-3 instead of any X/Y/Z.
AVX512 => Broken implementation. Stuck with the old way of strictly following X,Y,ZMM conformity.
^== Which will be fixed with Willowcove onwards, it will only be AVX3 with WLC.

 

[TheGiant]

The x-variants aren't going to be on the 272-nm(low power track library), but rather on mid-power/mid-perf(340-nm) to high-perf(408-nm).
Gaming isn't the concern for any of the corex models. It is all about crunching those universal-emulation simulations.

Potentially, looking at SkylakeX, at four 256-bit units that can fuse into two AVX512 for SunnycoveX. Port0/Port1 being the first AVX512 unit and Port5/6 being the second AVX512 unit.

1x full-ISA AVX512 on average for older SkylakeX/Sunnycove to 2x full-ISA AVX512 on SunnycoveX. Anything to get to full throughput across all AVX3 levels: 128b(4), 256b(4), 512b(2). Which I believe the ultra-wide WillowcoveX(&Willowcove-client) will solve.

that avx would be starved even with ddr5 8CH
I am getting sick of it, with my CFDs every new CPU is more powerful yet they didnt solve mem bandwitch or frequency or ECC check...

about that gaming I wouldn't be so sure, AMD TR3 is coming

it will perform well in apps and gaming too, so except very few avx512 uses it will be the intel lineup killer
and with that unified l3, which definitely helps latency they will get even close to ringbus desktop models

 

[Ajay]

Any news of the x variants?
Is Intel working on improving gaming performance or better say latency?

No news. If Intel follows recent patterns, the "X" platform will be based off the server CPU not the client CPU. The client CPU will likely continue to exceed the performance of the 'X" series in games.

 

[Ajay]

Is it Sunny Cove or Willow Cove? It isn't a drastically new uarch regardless.

edit: okay I'm going to retract that statement since it looks like Sapphire Rapids is actually Willow Cove:

News | Latest tech news & rumours | Trusted Reviews

Read about the latest tech news and developments from our team of experts, who provide updates on the new gadgets, tech products & services on the horizon.

www.theinquirer.net

Looks like Sapphire Rapids is turning out more like Tiger Lake-SP than anything else.

The INQ article refers to this info on WikiChip: https://fuse.wikichip.org/news/2336...r5-pcie-5-0-for-2021-granite-rapids-for-2022/

With much of the infos based on leaked slides from Intel (May) and Huawei (Russian event):



And...



Obviously, some of the info is old already. Cooper Lake will cover (probably volume wise) both ICL-SP and SR-SP. The article doesn't indicate with architecture ('coves) will be used in any of the CPUs. Some variant of Willow cove seems likely for SR, but we have no confirmation. I'm curious if the 10nm parts will use a different topology than the Skylake Mesh system.

 

[Carfax83]

that avx would be starved even with ddr5 8CH
I am getting sick of it, with my CFDs every new CPU is more powerful yet they didnt solve mem bandwitch or frequency or ECC check...

I'm curious, but if AVX2/AVX-512 is really that bandwidth starved, why do we still get large performance increases from using it?

For example, in the Icelake preview:





That's a pretty big increase from using AVX2 and especially AVX-512, on platforms that have relatively low memory bandwidth.

 

[DrMrLordX]

This is all speculative.

Generally-speaking, I trust TheInq. I don't necessarily like them, but I put them above a source like Adored. Even if the info they're citing dates back to May. It still mostly lines up: Golden Cove shouldn't show up until 7nm chips are ready, which looks like 2022. Everything before that (including possibly Granite Rapids) looks to be some 10nm variant.

@Carfax83

3DPM in general does not use main memory for much of anything. It creates random particle positional/movement data and then processes the data according to different particle movement models. There are six different models it uses. We had a pretty good thread on that around here with Dr. Cutress not so long ago, which is why you now have a v2.1 instead of the original, horribly-unoptimized 3DPM.

If I recall correctly, the working set is not that large. It's a more raw test of CPU performance independent from memory bandwidth/latency. Cache performance plays a much larger role. You would need a benchmark with a larger working set, like maxed-out Linpack, to see the effects of memory bandwidth starvation (if any).

 

[Carfax83]

3DPM in general does not use main memory for much of anything. It creates random particle positional/movement data and then processes the data according to different particle movement models. There are six different models it uses. We had a pretty good thread on that around here with Dr. Cutress not so long ago, which is why you now have a v2.1 instead of the original, horribly-unoptimized 3DPM.

Would the same apply to Intel's SVT codecs? If you look at this link, Phoronix has a comparison benchmark of the before and after of the AVX2 performance enhancements in the first graph for SVT-VP9. You can see the 9900K for instance went from 57.83 to 176.91 FPS, a 3 fold increase.

And the low end Core i5 8400 had a slightly larger improvement from AVX2.

 

[Nothingness]

@Carfax83 If you want to see workloads using AVX2/512 and are bandwidth starved, you should look at prime95 and y-cruncher. Both are multi-threaded and run hand-tuned assembly language routines.

 

[DrMrLordX]

Would the same apply to Intel's SVT codecs?

I haven't looked at them or used them for anything, so i'm not 100% sure. But I agree with @Nothingness that y-cruncher in particular is an application where bandwidth starvation can be an issue. You can make it use up most of your RAM and even try to make it use your storage subsystem (eeek); in fact, the author of y-cruncher has more-or-less said that the benchmark tests your RAM/storage more than anything else beyond a certain number of positions. The whole point of y-cruncher was to try to set records calculating pi to a certain number of positions, which is only possible with massive amounts of fast storage and/or RAM. Those of us who calculate it to "only" 500 million digits or what have you aren't testing the limits of the application (but we are testing the speed of our CPUs).

 

[TheGiant]

Would the same apply to Intel's SVT codecs? If you look at this link, Phoronix has a comparison benchmark of the before and after of the AVX2 performance enhancements in the first graph for SVT-VP9. You can see the 9900K for instance went from 57.83 to 176.91 FPS, a 3 fold increase.

And the low end Core i5 8400 had a slightly larger improvement from AVX2.

the SVT is fantastic, i5 6600K does a job of 6950X before, not even talking about what monster became of 3900X
this time good job Intel

 

[TheGiant]

btw anyone leaks of macbook icelake/tigerlake?

 

[eddman]

Intel’s Entire 10th Gen Comet Lake Desktop CPU Lineup Leaked

These slides look suspicious to me.

Why do 9500, 9500T, 9700 and 9700T have HT?
Are they really going to use 6+2 dies for quad and even dual core models?!

 

[Gideon]

These slides look suspicious to me.

Why do 9500, 9500T, 9700 and 9700T have HT?
Are they really going to use 6+2 dies for quad and even dual core models?!

It's been rumored in multiple places that the i3 and i5 and i7 will get HT. That's also logical, as this would make the CPUs very competitive again. Pretty much go-to at every price point, if you do gaming the majority of the time. Productivity wise AMD would still be recommended (but the difference in low- and mid-range would be much smaller).
The i9 would still be in a really odd place though. It won't be any faster in gaming than the 8 core and those 2 extra cores would still lose quite badly to AMD's 12 (let alone 16) cores in all heavily threaded workloads.

AMD would probably still have to adjust some prices in the mid- and low end (at the very least 3600X and 3800x).

 

[maddie]

It's been rumored in multiple places that the i3 and i5 and i7 will get HT. That's also logical, as this would make the CPUs very competitive again. Pretty much go-to at every price point, if you do gaming the majority of the time. Productivity wise AMD would still be recommended (but the difference in low- and mid-range would be much smaller).
The i9 would still be in a really odd place though. It won't be any faster in gaming than the 8 core and those 2 extra cores would still lose quite badly to AMD's 12 (let alone 16) cores in all heavily threaded workloads.

AMD would probably still have to adjust some prices in the mid- and low end (at the very least 3600X and 3800x).

Yep, prices will have to be adjusted. Action - reaction. Where will it end?