Discussion Intel current and future Lakes & Rapids thread

[mikk]

Intel® CPU 0000 with UHD Graphics, LKF

CL_DEVICE_MAX_CLOCK_FREQUENCY 2500
CL_DEVICE_MAX_COMPUTE_UNITS 5

CL_DEVICE_MAX_CLOCK_FREQUENCY 500
CL_DEVICE_MAX_COMPUTE_UNITS 64

https://compubench.com/device.jsp?b...PU+0000+with+UHD+Graphics,+LKF&testgroup=info

First Lakefield entry. CPU frequency is surprisingly high for such a low power Soc, especially for an 0000 ES. It could be a misread because with two different CPUs it works differently than previous Atom generations.

 

[Dayman1225]

Intel held an "IDC" (Israel Development Centre) day, where they presented info on the Icelake based NNP-I, Ethernet 800 Series and a 2hr 45min presentation on how Icelake was made, plus a fab tour.

The Icelake NNP-I has been gutted of a graphics and display engine and instead, Intel have added specialized DSPs and ASICs to accelerate Inferencing. It uses the M.2 form factor and carries similar TDPs to the Icelake U series, it is currently sampling to large customers and will be put into HVM later this year. Speeds and feeds at launch.

All of the Core development is currently being done at IDC, Oregon's last design was Haswell/Broadwell, IDC developed Skylake and its derivatives, as well as Sunny Cove and beyond. Haifa team reportedly blames Oregon for the 10nm mess.

Sunny Cove development began 4 years ago.

Around 12% of Intel's employees are in Israel and they have a hand in nearly everything Intel develops.

Spoiler: Images

 

[OriAr]

It is well known fact here in Israel that Intel has a love affair with this country.
So I am not surprised at all by this.

 

[NostaSeronx]

Sunnycove/Willowcove are California(Folsom) and Oregon(Hillsboro/Portland) projects though. New bleeding edge core projects are only at Oregon(at OR/Hillsboro Fab) and California(at AZ/Chandler Fab). Only refreshes(ex: Kaby, Coffee, Whiskey, etc) and overhauls(ex: changing the encode/decode capabilities, inserting GPU revisions, etc) are handled by Haifa. imho, Haifa is busy with Mobileye at the moment.

 

[OriAr]

Sunnycove/Willowcove are California(Folsom) and Oregon(Hillsboro/Portland) projects though. New bleeding edge core projects are only at Oregon(at OR/Hillsboro Fab) and California(at AZ/Chandler Fab). Only refreshes(ex: Kaby, Coffee, Whiskey, etc) and overhauls(ex: changing the encode/decode capabilities, inserting GPU revisions, etc) are handled by Haifa. imho, Haifa is busy with Mobileye at the moment.

Mobileye is actually based in Jerusalem mostly, and as far as I know is still a company by itself (Even if it is a subsidiary of Intel) and is largely autonomous.

Intel has 5 centers in Israel:
Intel Haifa - The main development center, this is where Conroe, Sandy Bridge, Skylake and Ice Lake were developed. And looks like it'll stay the main development center for Intel's core for a while yet.
Intel Jerusalem - a secondary development center mainly centered around communication and software.
Intel Petah Tiqwa - A recently opened development center dedicated for wireless solutions.
Intel Yokneam - A secondary development center for hardware stuff (I don't really know)
Intel Qiryat Gat - Fab28, the manufacturing site for 10nm, used to manufacture 22nm (Haswell) too. Fab18 used to be here too (65 nm manufacturing).

I think Oregon and CA mainly focus on the GPU business these days, but I am not quite sure.

 

[jpiniero]

By the way, Intel recently added basic support for Tigerlake in the Linux IGP driver. I was wondering when they were going to do this.

 

[Tarkin77]

Intel has the big Ice Lake-SP Xeon die back

https://semiaccurate.com/2019/07/02/intel-has-the-big-ice-lake-sp-xeon-die-back/

 

[Markfw]

Intel has the big Ice Lake-SP Xeon die back

https://semiaccurate.com/2019/07/02/intel-has-the-big-ice-lake-sp-xeon-die-back/

Nothing there to read. And whats with the huge letters ?

 

[Tarkin77]

Nothing there to read. And whats with the huge letters ?

sorry... fixed the large font. Article is behind a paywall. Its about core count and bringup (cant reveal details ... i have a student level subscription)

 

[Markfw]

sorry... fixed the large font. Article is behind a paywall. Its about core count and bringup (cant reveal details ... i have a student level subscription)

Nobody except subscribers can read it, so its a pretty worthless link.

 

[DrMrLordX]

If it's still the 26c chip then it's not that big of a deal. Larger than that though, might be interesting.

 

[Dayman1225]

If it's still the 26c chip then it's not that big of a deal. Larger than that though, might be interesting.

Its larger

 

[DrMrLordX]

Its larger

Hmmm 64c?

 

[Dayman1225]

Hmmm 64c?

Not quite that large lol.

 

[jpiniero]

Hmmm 64c?

Originally it was meant to top out at 38, but that was monolithic. I don't know if that means that they are doing dual die models with the 26 core maybe, like Cooper.

 

[DrMrLordX]

Not quite that large lol.

I'm shocked. Oh wait, no I'm not.

Originally it was meant to top out at 38, but that was monolithic. I don't know if that means that they are doing dual die models with the 26 core maybe, like Cooper.

Could be. Hopefully it works out better than Cascade Lake-AP.

 

[inf64]

Originally it was meant to top out at 38, but that was monolithic. I don't know if that means that they are doing dual die models with the 26 core maybe, like Cooper.

I think it's 2x28C dice with 26 cores active on each.

 

[jpiniero]

I think it's 2x28C dice with 26 cores active on each.

That does sound about right, but you are talking about max of course. If they did that, they probably only get maybe two 26 core dies per wafer. How far will they have to cut for the typical die to be usable? And at that point, why bother when Rome is available?

 

[Dayman1225]

I think it's 2x28C dice with 26 cores active on each.

It is a larger monolithic die. Not dual die.

 

[TheGiant]

It is a larger monolithic die. Not dual die.

care to share any details ?

 

[JoeRambo]

Hopefully 8C of memory to feed the cores, L3 cache per core can stay the same as in Skylake-SP, just the core counts need to grow.

Anyone did "tile geometry" to see possible layouts and core counts?

 

[jpiniero]

care to share any details ?

The wafer either has 36 or 38, if they are sticking with the original plan and not anything like Cooper Lake. Those madmen at Intel are actually going to do it, imagine they are getting less than 1 fully enabled per wafer.

 

[TheGiant]

The wafer either has 36 or 38, if they are sticking with the original plan and not anything like Cooper Lake. Those madmen at Intel are actually going to do it, imagine they are getting less than 1 fully enabled per wafer.

I don't think they are stupid
they need to get their name soon as possible and with 38C icelake they get it even if they spend wafers for it, they need to show they can do it
now Intel has a name of having nothing except +++14nm+++
on the other hand, when they start really producing that 10nm HCC dies, they can tune that process, when they don't it never get tuned properly
and 8MemCH Icelake 38C with mid 3GHz turbo all core with optane things around- that is a serious stuff

 

[IntelUser2000]

Hopefully 8C of memory to feed the cores, L3 cache per core can stay the same as in Skylake-SP, just the core counts need to grow.

Anyone did "tile geometry" to see possible layouts and core counts?

Icelake-SP is 8 channels.

3 possibilities.

5x6 config like current generation: 26 cores, because for yet unknown reason non-core portion takes 4 spaces.

-6x6 with 32 cores
-6x7 with 38 cores: This was in early leaks, but not sure if this is true anymore.

 

[jpiniero]

Anyone want to guess when Intel fully announces the Icelake/Comet Lake U lineup? Figure it would have to be soon. Sunday would be pretty petty.