Discussion Intel current and future Lakes & Rapids thread

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NTMBK

Lifer
Nov 14, 2011
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Okay, so Skylake has 168 vector registers already. If each AVX-512 register takes 2 vector registers, and there's 32 AVX-512 registers, then it would fit into the existing register file with room to spare. It leaves less room for rescheduling, but with 32 registers you would hope that the compiler has more flexibility to schedule sensibly (and each op takes up two ports, so the OoO engine needs to find less parallelism to keep the core busy).
 

Dayman1225

Golden Member
Aug 14, 2017
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Intel will discuss several aspects of its 10nm node first unveiled in March. It sports FinFETs with a 7nm fin width at a 34nm pitch and a 46nm fin height made using self-aligned quadruple patterning
(Intel will be detailing their 10nm in December at IEDM)

That is different to what this Intel slide previously said
C8Gi6ieXkAAxf1f.jpg

Pitch of 34 Height of 53 vs the 34 and 46 mentioned in that article.

DMiOt_SW4AEHICO.jpg:large


Twitter Thread where I seen this
 

Dayman1225

Golden Member
Aug 14, 2017
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I probably should have added it was somewhat recent - I didn't see it posted here before so I went ahead and posted it.

Also Intel Q3 results on Thursday - Likely to give update on 10nm products in their financial call. Hopefully specifically mention Cannonlake and give us a more exact date(I.E December 10th) instead of EOY2017
 
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TheF34RChannel

Senior member
May 18, 2017
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I probably should have added it was somewhat recent - I didn't see it posted here before so I went ahead and posted it.

Also Intel Q3 results on Thursday - Likely to give update on 10nm products in their financial call. Hopefully specifically mention Cannonlake and give us a more exact date(I.E December 10th) instead of EOY2017

As a desktop user I don't have an interest in CNL, and would rather hear about ICL ;)
 
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Dayman1225

Golden Member
Aug 14, 2017
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As a desktop user I don't have an interest in CNL, and would rather hear about ICL ;)

I wanna see if they update Core M with CNL parts - and the perf uplift with Gen 10 graphics and 40Eus. That's all really.

Though isn't Icelake Y/U expected sometime in H2 2018 ? I'd like to see that too.
 

IntelUser2000

Elite Member
Oct 14, 2003
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I wanna see if they update Core M with CNL parts - and the perf uplift with Gen 10 graphics and 40Eus. That's all really.

I'm not sure what's the point of having 40EUs on a 5.2W chip. It'll still likely underperform 14nm 15W parts anyway. What's more certain is that there will be some nice battery life and potential form factor improvements due to integrated voltage regulator.

Though isn't Icelake Y/U expected sometime in H2 2018 ? I'd like to see that too.

If the Y is coming in December of this year, Icelake Y is going to end up December of next year, if not later. If they decide Y is going to be the only CNL product, then Icelake U coming perhaps holiday of 2018 is possible.

I don't think we'll see any Icelake parts before Q1 of 2019. And I'm not talking about CES in January. Solid Q1.


Looking at their process graph, there's a bigger gap between 10+ and 10++ than 10 is with 10+. That means 10++ is going to take a longer time to come than 10+ did when comparing to its predecessor.

I hope the reduction in fin height were done for good reasons. Like being easier to manufacture. Whatever technical benefits an aggressive process might have had can be easily overcome by being overly difficult to manufacture it. If the shorter fin height means we end up with a better product due to having more realistic goals, then the decision is justified.
 
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Dayman1225

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Aug 14, 2017
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Oh no - I don't expect a Core M chip with 40EUs. Just a CNL Core M chip with Cut down EUs I suppose.

Though I don't think Intel really counts CNL as a real "gen" for Y/U I feel ICL Y/U would come out about a year after KBL R and not follow CNL, but who knows...
 

Dayman1225

Golden Member
Aug 14, 2017
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During Intel's Earnings call right now - BK the CEO said. Low volume 10nm EOY 2017 - Ramp throughout H1 2018 and High Volume in H2 2018.
 

Yotsugi

Golden Member
Oct 16, 2017
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During Intel's Earnings call right now - BK the CEO said. Low volume 10nm EOY 2017 - Ramp throughout H1 2018 and High Volume in H2 2018.
DOA as long as GloFo continues their (pretty decent) execution on 7LP.
Like, why the hell HVM only H2 2018?
Are they nuts?
The time is against them.
 

jpiniero

Lifer
Oct 1, 2010
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During Intel's Earnings call right now - BK the CEO said. Low volume 10nm EOY 2017 - Ramp throughout H1 2018 and High Volume in H2 2018.

That pretty much confirms the Digitimes rumor. You probably won't actually even see the dual core Cannonlake on shelves until Q3/4 next year.