Thunder 57
Diamond Member
- Aug 19, 2007
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DrMrLordX
Lifer
- Apr 27, 2000
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Not sure why I'm supposed to care about 3700X benchmarks in 2023 but hey whatever.
Cope so hard it's made the thread go back in time.
Not exactly a show of confidence in Intel 20A
Looks like that Intel internal conflict over the node of ARL Raichu was talking about a week or two ago has been resolved.
Edit: oh also apparently it uses N3B.
Looks like that Intel internal conflict over the node of ARL Raichu was talking about a week or two ago has been resolved.
Edit: oh also apparently it uses N3B.
Maybe CapFramex dude's suggestion for 3700X owners is to ditch their PC and just build a 9900K or 9900KS system instead of going with something like 5800X3D. Folks who shoot before they think are very likely to do that in panic (Oh no! Ma CPU sucks! Gotta get the faster 9900K!).
Ok just to make me not look like a lunatic lol, there was a tweet attached to this comment by Xino, but he has since deleted it, so ig it disappeared off my comment as well. It was about ARL-H moving to TSMC N3B from 20A
coercitiv
Diamond Member
- Jan 24, 2014
- 7,359
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Folks, I strongly suggest we stop posting simple Twitter links. Take a screenshot, add the link to the pic or paste bellow. Not only are twitter leaks ephemeral in particular, but recently any tweet can be considered hard to reach by many people. If not today, then tomorrow.
DrMrLordX
Lifer
- Apr 27, 2000
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Well yes, the platform differences there are pretty stark. Got a 9900K? No real upgrade path. Got a 3700X? Get a 5800X3D. Also I went back and looked at launch reviews for the 3700X and it wasn't exactly winning many gaming benchmarks anyway, so revisiting that fact in 2023 didn't really make much sense?
Still don't know why that would be useful in a thread about Intel current and future CPUs.
Seconded. I don't log in to Twitter, so now the entire service is unbrowsable for me.
uzzi38
Platinum Member
- Oct 16, 2019
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Intel Resumes Shipping Xeon MCC Processors After Bug is Mitigated
Intel is also distributing the microcode fix to partners.
And there we go, that's that. SPR-MCC is shipping once again.
DrMrLordX
Lifer
- Apr 27, 2000
- 22,912
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Oh goody, more mitigations. What kind of performance penalties will users pay for that?Intel Resumes Shipping Xeon MCC Processors After Bug is Mitigated
Intel is also distributing the microcode fix to partners.www.tomshardware.com
And there we go, that's that. SPR-MCC is shipping once again.
poke01
Diamond Member
- Mar 8, 2022
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Not every fix has regressions
SRF looks like it's going to be pretty small all things considered
144 cores, 144MB L2, and 108MB L3
Using Intel 4, that's gonna give us:
(144/4) x 6.2mm^2 (cores+L2) =~220
(144/4) x 1.15mm^2 (L3) = ~40
I'm guessing each 'block' of the SRF layout is going to be ~7.5mm^2, accounting for the mesh, tweaks in Crestmont vs SRG, but also potential slight density uplift in Intel 3. Using 36 core cluster active, 4 clusters for MC, and 2 for dead core clusters for yields, we could be getting a 6x7 square layout for ~315 mm^2. Accounting for EMIB too, I don't think SRF compute tile is going to be too much larger than 350 mm^2 right?
Wouldn't mind if anyone checked my calculations either
6.2mm^2 for Crestmont was shown in the Zen 4C vs E-cores thread though, I'll link my exact comment later.
144 cores, 144MB L2, and 108MB L3
Using Intel 4, that's gonna give us:
(144/4) x 6.2mm^2 (cores+L2) =~220
(144/4) x 1.15mm^2 (L3) = ~40
I'm guessing each 'block' of the SRF layout is going to be ~7.5mm^2, accounting for the mesh, tweaks in Crestmont vs SRG, but also potential slight density uplift in Intel 3. Using 36 core cluster active, 4 clusters for MC, and 2 for dead core clusters for yields, we could be getting a 6x7 square layout for ~315 mm^2. Accounting for EMIB too, I don't think SRF compute tile is going to be too much larger than 350 mm^2 right?
Wouldn't mind if anyone checked my calculations either
6.2mm^2 for Crestmont was shown in the Zen 4C vs E-cores thread though, I'll link my exact comment later.SRF is going to be Intel 3 although I don’t know how much that’d change the calculations you’ve done.SRF looks like it's going to be pretty small all things considered
144 cores, 144MB L2, and 108MB L3
Using Intel 4, that's gonna give us:
(144/4) x 6.2mm^2 (cores+L2) =~220
(144/4) x 1.15mm^2 (L3) = ~40
I'm guessing each 'block' of the SRF layout is going to be ~7.5mm^2, accounting for the mesh, tweaks in Crestmont vs SRG, but also potential slight density uplift in Intel 3. Using 36 core cluster active, 4 clusters for MC, and 2 for dead core clusters for yields, we could be getting a 6x7 square layout for ~315 mm^2. Accounting for EMIB too, I don't think SRF compute tile is going to be too much larger than 350 mm^2 right?
Wouldn't mind if anyone checked my calculations either
adroc_thurston
Diamond Member
- Jul 2, 2023
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Size/upfront costs really-really do not matter in its primary markets.
Right now it has no hyperscaler wins that I know of.
Missing in the block calculation is area required for the mesh interconnect. Beyond that, the estimate for interface borders on all sides (EMIB and DDR5) seems a bit low. Looking at SPR, probably about 1.5mm around each edge is used by the interfaces? If we assume 16mm*19mm for the core logic (304mm^2 is close enough to your 315mm^2 number) and add 1.5mm on each edge that already brings it up to 418mm^2. And I expect that actual size is going to end up a fair bit larger than that.
You're right, I totally underestimated EMIB size, since you are adding to the edges.
I don't think you would add it to each edge though, since only 2 sides would need EMIB (to attach to the IO dies on each side).
16 x 19 would be 16 x 22 or 19 x 19, or 350-360 mm^2.
Mesh ~0.4mm^2 for GLC IIRC. My OG calculations would still be around the same (7.2 + 0.4).
The IMC was around the same size as a core cluster in SPR, but I wonder how much of that was because it had to be that big, or if they just had the space to make it that large since it was effectively a "tile".
I totally forgot about the DDR5 PHY, in SPR that was ~7mm^2
For the DDR5 PHYs though, the 'border width' is only roughly half that of the EMIB blocks. Adding ~0.8 to the adjacent sides of the EMIB sides.
16 x 22 becomes 17.6 x 22, 19 x 19 becomes 19 x 20.6, or just shy of 400mm^2.
This is assuming none of these sizes change between SPR and SRF, and ignoring Intel 3 vs Intel 7 scaling.
I don't think SRF is going to end up being a fair bit larger than that though. Where else can additional area come from? All the accelerators, IO, should be moved over to the IO tiles.
I'm not really interested in the sales of SRF.
I mean obviously I wish it sells decently well, A) so Intel doesn't continue financially falling and cutting projects and B) so we see more E-core server products in the future
But I think the engineering and design behind it is much more interesting.
Don't think it would change much tbh. I don't think SRG is going to implement the denser libs that are available tbh, because of how Intel handled denser libs in the past, and then just progressively used less and less dense options throughout 10nm.
Plus I think doing so might require a lot of extra time in redesigning. I heard architects have computerized systems that, given parameters, automatically select what libs to choose where and when in a core, but I still think a lot of man power would be required for verification and design, no?
I think the best benefit they are getting from Intel 3 is the perf/watt gain.
adroc_thurston
Diamond Member
- Jul 2, 2023
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why even.
It's kinda boring really, just a pile of Atom clusters on a standard Intel mesh.
Well I mean the whole point of that product is density so obviously they will.
WCCFtech lmao
(right column is threads, left is cores)
Slightly related, I think this architecture release cadence would make sense:
ARL - Lion Cove
PTL - Cougar Cove (minor improvement)
BSTL? - Panther Cove, or what ever the original arch in panther lake was.
???- Hopefully the next 'big' architecture shift (royal core), or a slight improvement over panther cove (an effective tick)
I think the rumors that PTL switched what arch it was using would be a negative, as in instead of using a 'new' core arch compared to LNC, it would be shifting over to a 'tick' generation core. Knowing Intel, it's best to assume a downgrade lol.
Don't think we will be seeing 'royal core' until 2027-2028. And even that might be a optimistic.
(right column is threads, left is cores)
Slightly related, I think this architecture release cadence would make sense:
ARL - Lion Cove
PTL - Cougar Cove (minor improvement)
BSTL? - Panther Cove, or what ever the original arch in panther lake was.
???- Hopefully the next 'big' architecture shift (royal core), or a slight improvement over panther cove (an effective tick)
I think the rumors that PTL switched what arch it was using would be a negative, as in instead of using a 'new' core arch compared to LNC, it would be shifting over to a 'tick' generation core. Knowing Intel, it's best to assume a downgrade lol.
Don't think we will be seeing 'royal core' until 2027-2028. And even that might be a optimistic.
Boo. You could downplay anything Intel releases using that logic. GNR? Just a pile of bloated cores on a standard Intel mesh.
Cuz Intel's financials are just that much more interesting?
I have no faith they will. We will see ig.
'Obviously' Intel should have designed the E-cores in ADL/RPL to use at the very least, HP cells, but they didn't.
Would cut down power consumption and area marginally if they did, I'm guessing.
adroc_thurston
Diamond Member
- Jul 2, 2023
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It is what it is, AmpereOne is also getting roadkilled in scale-out favela wars.
It and EMR actually get really fat unified LLCs (albeit slow); that's interesting.
Well, more interesting than 144 meh atoms on a stick.
It's not leadership core/thread density and power isn't anything too impressive either soooo...
The product originally targeted N3 so obviously they will.
Tall cell spam ends circa i3, really.
EMR looks to be interesting because of that, but GNR only seems to be interesting because of the new node. Other large improvements don't seem to be present (other than perf metrics, but I'm referring to structure and parts of the CPU). Based on Pat's comments about the new core in GNR, I thought the core (LNC) might be very interesting, but all I'm hearing is RWC+ now a days. Not that GNR as a whole isn't interesting, just that I think SRF is just as interesting.
While SRF won't take any 'overall' crowns- it might be able to take it in one scenario- lowest power draw per thread at a certain (almost certainly low) performance threshold.
Read elsewhere what cloud customers are mainly after is efficiency at a certain level of performance they can license to their customers on a core-by-core basis. While GNR might be more efficient under heavy load at higher clocks, the narrower SRG cores should be able to take the lead at lower power levels, like GRC does over GLC.
Core density is great as well, but certain cloud providers are having second thoughts on high core density Bergamo because of rising costs related to higher core counts - AWS
First time I'm hearing SRF targeted N3. Thought LNC and SKM were the cores originally targeting N3, with RWC/Crestmont/SRG were originally targeting Intel 7nm/Intel 4.
I always thought that LNC was targeting Intel 3 + TSMC 3nm initially, as a 'tock' to RWC in MTL, so I think it's very believable tall cell spam ended there- with LNC+SKM.
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