Discussion Intel current and future Lakes & Rapids thread

[nicalandia]

In theory, there's no technical reason stopping Intel from making such a product. Whether they bother to do so is another matter.

It was his premises that was wrong. He said. Look at Crestmont Cluster it's as small as Redwood Cove so AMD is in trouble. The thing is... The Cluster is actually about 12% larger than the Redwood Cove core and neither of them are as area efficient as AMD Zen4/Zen4c

 

[coercitiv]

It was his premises that was wrong.

We usually care about the premise being wrong when it changes the conclusion. Packing a huge amount of E cores in a single product is still possible. Whether that would seriously threaten Zen4c is another talking point.

 

[nicalandia]

We usually care about the premise being wrong when it changes the conclusion. Packing a huge amount of E cores in a single product is still possible. Whether that would seriously threaten Zen4c is another talking point.

They can't pack 112 Clusters the size of 6 mm^2 on a CPU. His premise was that they would pack 448 Crestmont CPUs on a single CPU package. If they could package 112 Cluster they can package 112 Redwood Cove Cores on the same size.

 

[Exist50]

It was his premises that was wrong. He said. Look at Crestmont Cluster it's as small as Redwood Cove so AMD is in trouble. The thing is... The Cluster is actually about 12% larger than the Redwood Cove core and neither of them are as area efficient as AMD Zen4/Zen4c

I think quibbling over a few percent isn't worth the time of day. But if you're going to do that, consider that server RWC will have to be larger for more AVX/AMX support.

And why do you think it's not as area efficient as Zen 4/4c? Crestmont should pretty easily win against at least Zen 4, if not likely 4c as well.

 

[Exist50]

If they could package 112 Cluster they can package 112 Redwood Cove Cores on the same size.

Isn't GNR rumored to come with up to 128 cores active, and 150 cores printed? At a 4:1 ratio, that would mean 512 Crestmont cores, which would actually imply that he's already factoring the client area difference in.

 

[moinmoin]

Isn't GNR rumored to come with up to 128 cores active, and 150 cores printed?

What kind of die and package size are we talking about there? That part would need to be huuuuge going by SPR's size.

 

[nicalandia]

Isn't GNR rumored to come with up to 128 cores active, and 150 cores printed? At a 4:1 ratio, that would mean 512 Crestmont cores, which would actually imply that he's already factoring the client area difference in.

True, I forgot about Granite Ridge. 128 Cores will be impressive indeed.

 

[nicalandia]

What kind of die and package size are we talking about there? That part would need to be huuuuge going by SPR's size.

Multiply 6 mm^2 by 150 printed cores. Give it an additional 20% due to Mesh Interconnect/Memory/Logic So about 1,100 mm^2. Current SPR-SP is about 1,600 mm^2

 

[LightningZ71]

Down to a certain level, it's always going to be the case that you can use 4 cut down cores to outperform a same-size single core that's optimized for single thread throughput. As is reasonably well known in the business, each "last 5%" of performance costs an additional 50% of the total size of the processing core. There are two ways to fight back. You can join the club and use cut-down cores of your own, or, you can make your single thread throughput optimized cores wider and more intelligent and support more total throughput by enabling features like STM4 (I hope I don't bettlejuice this thread by mentioning it) and pay the price in security vulnerabilities and their mitigations in addition to failed speculative execution costs when you go really deep with out of order windows. There are always going to be cases where you can use hundreds of threads on a single server in the era of virtual machines and "cloud" app services. Having a ton of isolated hardware cores will always have it's advantages.

I'm not particularly worried about AMD in competing with this concept. They have the ability to pivot to it any time they want. I'm also not worried about the features as a service model for them either as they will likely have to move in that range with the integration of the Xylinx IP.

What a lot of people don't realize is that these dedicated functional units often include IP that the chip manufacturer doesn't fully own. To cover the licensing costs of that IP, they will either have to pay up front and roll that into the purchase price of the chip, or, they will pay as it is enabled and leave it dark on the chip when it isn't. It's much cheaper to develop a single mask and print a million chips with several percent of dark silicon that's only rarely enabled than it is to make half a dozen different masks to produce a variety of different chips. It's been going on in the industry for decades. We're only just now getting to the point where they can enable them dynamically in a way that they feel is secure and can't be easily hacked. Pluton and SGX don't just protect you from hackers, it protects these concepts from users trying to fully enable parts that they already have in their possession. And, with things like DMCA, it's illegal for you to try to circumvent that protection mechanism because it has other uses that that would infringe. AMD will be doing the same thing themselves. Why wouldn't they? Even industry wants this. It's much easier to pay for a software feature upgrade than to rip out hundreds and hundreds of servers to swap processors or completely replace at the cost of a fortune in labor and equipment, so it gives them a longer life cycle on their existing installed equipment (in the future when these technologies exist). It also allows them to pivot away from it when something better comes along or the business they are working in slows down and less is needed.

 

[Doug S]

I think you're being paranoid. /s

Spoiler

View attachment 71531

Buying something over time isn't the same as having a subscription for a feature. The above is no different than leasing a car, which has been around forever.

What I'm talking about is stuff like paying a monthly or yearly subscription fee to enable heated seats rather than paying say $500 extra when you buy the car. Stop paying, and you have cold seats.

 

[Markfw]

Buying something over time isn't the same as having a subscription for a feature. The above is no different than leasing a car, which has been around forever.

What I'm talking about is stuff like paying a monthly or yearly subscription fee to enable heated seats rather than paying say $500 extra when you buy the car. Stop paying, and you have cold seats.

Another example. For those that don't know, you can have your own modem/router and stop paying the $14 a MONTH RENTAL FEE. tHE ONE IS GOT IS THE exact SAME PIECE OF HARDWARE THEY WERE "RENTING" FOR MANY YEARS, AND AT $150 it pays for itself in a year.

Sorry about the caps, not going to retype.

So anybody that tries this on me, AMD, Intel or otherwise will lose my money.

 

[moinmoin]

What a lot of people don't realize is that these dedicated functional units often include IP that the chip manufacturer doesn't fully own. To cover the licensing costs of that IP, they will either have to pay up front and roll that into the purchase price of the chip, or, they will pay as it is enabled and leave it dark on the chip when it isn't. (...) AMD will be doing the same thing themselves.

Actually since Zen's introduction with some of the embedded chips AMD already offers integrated 10GbE interfaces that are not enabled with other chips using the exact same die. So yes, AMD already is doing the same on a hardware level.

 

[nicalandia]

So anybody that tries this on me, AMD, Intel or otherwise will lose my money.

So what's the Alternative? Open Source RISC-V CPUs for the Win? I would chose from the "Leser of The Evils" and that will Always be AMD.

 

[coercitiv]

Buying something over time isn't the same as having a subscription for a feature.

In this case it's one and the same: they are selling you the hardware bundled with a ~$25 subscription. Anyway, it was more intended as a joke on things to come, not quite adequate for this thread.

 

[Markfw]

So what's the Alternative? Open Source RISC-V CPUs for the Win? I would chose from the "Leser of The Evils" and that will Always be AMD.

So far I have not seen AMD do this, but if they do, then I would have to choose the lesser of 2 evils. Like it or not, too many things rely on Windows. I do most of my DC work in linux for this reason.

 

[Geddagod]

Isn't GNR rumored to come with up to 128 cores active, and 150 cores printed? At a 4:1 ratio, that would mean 512 Crestmont cores, which would actually imply that he's already factoring the client area difference in.

Isn't 128/150 cores a pretty large amount of the die size remaining disabled? Especially since this is also aiming for chiplets. I thought the rumor was 128 max, and then some cores could be disabled for the top sku in order for yields to work out.

 

[LightningZ71]

Actually since Zen's introduction with some of the embedded chips AMD already offers integrated 10GbE interfaces that are not enabled with other chips using the exact same die. So yes, AMD already is doing the same on a hardware level.

Yeah, those 10Gbe macs on Zepplin that you only ever see on the embedded versions are a nice touch. They also explain why the embedded versions typically have a worse price/performance than the desktop chips have.

 

[Exist50]

Isn't 128/150 cores a pretty large amount of the die size remaining disabled? Especially since this is also aiming for chiplets. I thought the rumor was 128 max, and then some cores could be disabled for the top sku in order for yields to work out.

Ah, I found the original source. I misremembered slightly. Raichu claims max GNR is 3x48c tiles, with a max 128c active. So 128 active/144 printed.

https://twitter.com/x/status/1590767694126911488

But yeah, that's still a pretty decent amount of silicon disabled. I wonder if 128 is the cap due to yields, or some other limit. It would be kinda funny if the best dies went into something like a 2x48c=96c config.

 

[Exist50]

Also, while skimming through Raichu's posts for that source, I came across this bizarre tidbit.

https://twitter.com/x/status/1590761980838936576

Would Intel seriously have a Panther Cove and Panther Lake but not use Panther Cove in Panther Lake? Or were previous leaks about the Panther Cove name wrong, and it's actually Cougar Cove?

 

[Geddagod]

Ah, I found the original source. I misremembered slightly. Raichu claims max GNR is 3x48c tiles, with a max 128c active. So 128 active/144 printed.

https://twitter.com/x/status/1590767694126911488

But yeah, that's still a pretty decent amount of silicon disabled. I wonder if 128 is the cap due to yields, or some other limit. It would be kinda funny if the best dies went into something like a 2x48c=96c config.

I think it's probably a yield thing, I'm willing to bet the next generation will utilize the full 144 cores (unless the next gen xeon is "new" generation after granite rapids, unlike sapphire rapids > emerald rapids). Doesn't Sapphire Rapids do the same thing, max out with 56 cores with Emerald Rapids going up to 60? Could be misremembering that though, maybe Sapphire Rapids does the full maxed out 60 as well.

 

[Geddagod]

I'm guessing this is what a Granite Rapids is going to look like based on the leaks we have so far. It might be completely inaccurate, but at least it was fun to make : )

 

[Exist50]

Doesn't Sapphire Rapids do the same thing, max out with 56 cores with Emerald Rapids going up to 60? Could be misremembering that though, maybe Sapphire Rapids does the full maxed out 60 as well.

There've been rumors of a single 60c SKU, but if it exists at all, I don't expect it will be for anything more than marketing. And I think Emerald Rapids is different silicon altogether, not just a new stepping of SPR or something.

I'm guessing this is what a Granite Rapids is going to look like based on the leaks we have so far. It might be completely inaccurate, but at least it was fun to make : )

So the more I think about it, the more convinced I become that they must have put mem controllers on the compute dies. There'd be no reason to push the IO dies to the far ends otherwise.

 

[IntelUser2000]

But yeah, that's still a pretty decent amount of silicon disabled. I wonder if 128 is the cap due to yields, or some other limit. It would be kinda funny if the best dies went into something like a 2x48c=96c config.

Remember Icelake-SP was forever rumored to be 38 cores? And then they released 40 cores? Now Sapphire Rapids is 60, when we thought it was 56 max.

I'm pretty sure they'll get something like a 138 or even 140 core SKU out. It's like a pretty open "secret" to keep competitors guessing I presume?

 

[Exist50]

Remember Icelake-SP was forever rumored to be 38 cores? And then they released 40 cores? Now Sapphire Rapids is 60, when we thought it was 56 max.

Even if those SKUs exist, if the volume is so low that you'll never see one in a cloud or large enterprise offering, does it really matter? I don't think the people/companies that actually buy these chips care much about a top-bin Phoronix dick-measuring contest.

And the gap with GNR would be much bigger than either of those two, which makes me wonder if there's anything beyond just yields in play. Maybe it's pure coincidence, but that's a nice even power of two.

 

[IntelUser2000]

You are saying they'll be used in very small amounts but I'm saying there's a very good chance it'll exist which do not contradict each other.

Otherwise, the story would be that the 128 core version(56 core in SPR's case) would play the same role. In that line, for EMR I wouldn't be too surprised if the top chip is based on even bigger dies, like something that would end up with 70-something cores.

It isn't the first time they did this. Either they are being very conservative until the last moment, and/or they are doing it for competitive reasons, because the last few % matters. Worst case is that it's 128 cores, and if they execute flawlessly maybe they can enable quite a few more which is a bonus.

Which is a good trend, since it means they aren't overpromising anymore. I think the new mentality is also representative of better management because you need the conservative expectations so they can better meet their goals.

Raptorlake: "Up to double digit performance boost"